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Features
* Programmable System Clock with Prescaler and Five Different Clock Sources
- Up to 8-MHz Crystal Oscillator (System Clock) - 32-kHz Crystal Oscillator - RC-oscillator Fully Integrated - RC-oscillator with External Resistor Adjustment - External Clock Input Wide Supply-voltage Range (2.4 V to 6.2 V) Very Low Halt Current 4-Kbyte EEPROM, 256 x 4-bit RAM 8 Hard and Software Interrupt Priority Levels Up to 10 External and 4 Internal Interrupts, Bit Wise Maskable with Programmable Priority Level Up to 34 I/O Lines I/O Ports - Bit Wise Configurable with Combined Interrupt Handling (for Serial I/O Applications) 2 x 8-bit Multifunction Timer/Counters Coded Reset and Watchdog Timer Power-on Reset and "Brown Out" Functions Various Power-down Modes Efficient, Hardware-controlled Interrupt Handling High Level Programming Language qFORTH Comprehensive Library of Useful Routines Windows(R) 95/Windows NT(R) Based Development and Programmer Tools
* * * * * * * * * * * * * * *
MARC4 4-bit MTP Universal Microcontroller ATAM510
Description
The ATAM510 is a Multi-time Programmable (MTP) microcontroller which is pin and functionally compatible to Atmel's ATAR510 mask programmable microcontroller. It contains an EEPROM, RAM, up to 34 digital I/O pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer, an interval timer, 2 x 8-bit multifunction timer/counter modules and a versatile software configurable on-chip system clock module.
Rev. 4711B-4BMCU-01/05
Figure 0-1.
Block Diagram
TE SCLIN OSCIN OSCOUT AVDD VSS NRST VDD TIM1
Test Sleep
System clock
Real time clock
Master reset
ROM
4K x 8 bit
RAM
256 x 4 bit
Timer/ counter Watchdog Prescaler Timer 1 Timer 0 Melody & buzzer
MARC4
4-bit CPU core I/O bus
I/O I/O
4 4 4
I/O I/O
4
I/O
Interrupt & reset
4
I/O
Interrupt
I/O
I/O
Interrupt
I/O
4
4
2
4
Port 0 Port 1 Port 5 Port 7
Port A
Port B
Port C
Port 6
Port 4
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1. Pin Configuration
Figure 1-1. Pinning SSO44
AVDD OSCIN OSCOUT SCLIN BPC3 BPC2 NRST BPB2 BPA0 BPB1 BPA1 BPB3 BPB0 BPA2 21 BP11 24 BPA3 BP10 22 23
BP71
BP72
BP73
BP70
44
43
42
41
BP61
BP60
PM
36
34
32
39
40
37
38
ATAM510
5
7
2
1
3
4
6
8
9
10
11
12
13
14
15
30
35
33
31
BPC1 16
29
17
28
BPC0 18
27
19 BP13
26
TIM1
VSS
BP53
BP52
BP51
BP00
BP50
BP43
BP42
BP41
BP40
BP03
BP02
VDD
BP01
Table 1-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Pin Description
Symbol VSS BP53 BP52 BP51 BP50 VDD BP43 (NBUZ) BP42 (BUZ) BP41 (T0OUT1) BP40 (T0OUT0) BP03 BP02 BP01 BP00 TIM1 BPC1 TE BPC0 BP13 Function Circuit ground I/O line of high current Port 5 - bit wise configurable I/O line of high current Port 5 - bit wise configurable I/O line of high current Port 5 - bit wise configurable I/O line of high current Port 5 - bit wise configurable Power supply voltage +2.2 V to +6.2 V High current I/O line BP43 of Port 4 - configurable or buzzer output NBUZ High current I/O line BP42 of Port 4 - configurable or buzzer output BUZ I/O line BP41 of Port 4 - configurable or timer/counter I/O T0OUT1 I/O line BP40 of Port 4 - configurable or timer/counter I/O T0OUT0 I/O line of Port 0 - automatic nibble wise configurable I/O line of Port 0 - automatic nibble wise configurable I/O line of Port 0 - automatic nibble wise configurable I/O line of Port 0 - automatic nibble wise configurable Dedicated I/O for Timer 1 I/O line of Port C - bit wise configurable I/O Test mode input, used to control production test modes (internal pull-down) I/O line of Port C - bit wise configurable I/O I/O line of Port 1 - automatic nibble wise configurable
TE
BP12
20
25
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Table 1-1.
Pin 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin Description
Symbol BP12 BP11 BP10 BPA3 BPA2 BPA1 BPA0 NRST OSCOUT OSCIN AVDD BPC2 BPC3 BPB0 BPB1 BPB2 BPB3 BP60 BP61 SCLIN PM BP73 BP72 BP71 BP70 Function I/O line of Port 1 - automatic nibble wise configurable I/O line of Port 1 - automatic nibble wise configurable I/O line of Port 1 - automatic nibble wise configurable I/O line of Port A - bit wise configurable, as inputs for port monitor module and optional coded reset inputs I/O line of Port A - bit wise configurable, as inputs for port monitor module and optional coded reset inputs I/O line of Port A - bit wise configurable, as inputs for port monitor module and optional coded reset inputs I/O line of Port A - bit wise configurable, as inputs for port monitor module and optional coded reset inputs Reset input (/output), a logic low on this pin resets the device. An internal watchdog or coded reset can generate a low pulse on this pin 32-kHz or 4-MHz quartz crystal output pin 32-kHz or 4-MHz quartz crystal input pin Analog power supply voltage +2.2 V to +6.2 V I/O line of Port C - bit wise configurable I/O I/O line of Port C - bit wise configurable I/O I/O line of Port B - bit wise configurable I/O and as inputs for port monitor module I/O line of Port B - bit wise configurable I/O and as inputs for port monitor module I/O line of Port B - bit wise configurable I/O and as inputs for port monitor module I/O line of Port B - bit wise configurable I/O and as inputs for port monitor module I/O line of Port 6 - bit wise configurable I/O or as external programmable interrupts I/O line of Port 6 - bit wise configurable I/O or as external programmable interrupts External trimming resistor or external clock input MTP program mode enable pin (internal pull-down) I/O line of high current Port 7 - bit wise configurable I/O line of high current Port 7 - bit wise configurable I/O line of high current Port 7 - bit wise configurable I/O line of high current Port 7 - bit wise configurable
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2. MARC4 Architecture
2.1 General Description
The functionality, programming and pinning of the ATAM510 is compatible with the ATAR510 mask programmable microcontroller from Atmel. All on-chip modules are addressed and controlled with exactly the same programming code, so that a program targeted for the ATAR510 can be read directly into the ATAM510 and will operate in the same fashion. The MARC4 microcontroller consists of an advanced stack-based 4-bit CPU core and on-chip peripherals. The CPU is based on the Harvard architecture with physically separate program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus, are used for parallel communication between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high-level programming language qFORTH. The core includes both an expression and a return stack. This architecture enables high-level language programming without any loss of efficiency or code density. Figure 2-1. MARC4 Core
MARC4 CORE
Reset Program memory PC X Y SP RP Reset Clock Instruction bus Memory bus Instruction decoder System clock Interrupt controller I/O bus CCR ALU TOS RAM 256 x 4-bit
Sleep
On-chip peripheral modules
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2.2
Components of MARC4 Core
The core contains ROM, RAM, ALU, a program counter, RAM address registers, an instruction decoder and an interrupt controller. The following sections describe each functional block in more detail.
2.2.1
EEPROM The program memory (EEPROM) is programmed with the customer application program. The EEPROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4 Kbytes. The lowest user ROM address segment is taken up by a 512-byte zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL). The corresponding memory map is shown in Figure 2-2. Look-up tables of constants can also be held in EEPROM and are accessed via the MARC4's built-in table instruction. Figure 2-2. EEPROM Map of the ATAM510
FFFh FFFh 1F8h 1F0h 1E8h 1E0h
EEPROM
(4K x 8 bit)
1 E0h 1C 0h 180h
I NT 7 I NT 6 I NT 5 I NT 4 I NT 3 I NT 2 I NT 1 I NT 0
SCALL addresses
Z er o p age
140h 100h 0C 0h 080h
1FFh
Zero page
000h
020 h 018h 010h 008h 000 h
040h
008h 000h
$R E SE T $A U T O SL E E P
2.2.2
RAM The MARC4 contains 256 x 4-bit wide static random access memory (RAM). It is used for the expression stack, the return stack and data memory for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. Figure 2-3. RAM Map
RAM
(256 x 4-bit) Autosleep FCh FFh Global variables
Expression stack
3 0 TOS TOS-1 TOS-2 4-bit Expression stack Return stack SP
RAM address register:
X Y SP RP
04h 00h 07h 03h TOS-1
Return stack
11 0 RP
Global v variables 12-bit
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2.2.3 Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands from, and return their results to the expression stack. The MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data. Return Stack The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks, within the RAM, have a user definable location and maximum depth.
2.2.4
2.3
Registers
The MARC4 controller has seven programmable registers and one condition code register. They are shown in the following programming model.
2.3.1
Program Counter (PC) The program counter is a 12-bit register which contains the address of the next instruction to be fetched from the ROM. Instructions currently being executed are decoded in the instruction decoder to determine the internal micro-operations. For linear code (no calls or branches) the program counter is incremented with every instruction cycle. If a branch, call, return instruction or an interrupt is executed, the program counter is loaded with a new address. The program counter is also used with the table instruction to fetch 8-bit wide constants. Figure 2-4.
PC
7 0
Programming Model
11 0
Program counter
RP
7
0
0
0
Return stack pointer
SP
7 0
Expression stack pointer
X
7 0
RAM address register (X)
Y
3 0
RAM address register (Y)
TOS
3 0
Top of stack register
CCR
C
--
B
I
Condition code register
Interrupt enable Branch Reserved Carry/borrow
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2.3.2
RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or postdecremented if a nibble is removed from the stack. Every post-decrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack pointer has to be initialized with >SP S0 to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically pre-increments if an element is moved onto the stack, or it post-decrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized via >RP FCh. RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement addressing mode arrays in the RAM can be compared, filled or moved. Top of Stack (TOS) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. Condition Code Register (CCR) The 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow (C) The carry/borrow flag indicates that the borrow or carry out of the Arithmetic Logic Unit (ALU) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no affect on the C-flag. Branch (B) The branch flag controls the conditional program branching. Should the branch flag have been set by a previous instruction, a conditional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations.
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
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2.3.10 Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or while executing the DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI or SLEEP instruction.
2.4
ALU
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR). Figure 2-5. ALU Zero-address Operations
RAM
SP
TOS-1 TOS-2 TOS-3 TOS-4 CCR ALU
TOS
2.4.1
Instruction Set The MARC4 instruction set is optimized for the high level programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline which allows the controller to prefetch an instruction from EEPROM at the same time as the present instruction is being executed. The MARC4 is a zero-address machine, the instructions contain only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one and two byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions are only one byte long and are executed in a single machine cycle.
2.4.2
I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions the I/O bus allows a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section "Peripheral Modules". The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the MARC4 emulation.
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2.5
Interrupt Structure
The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the ROM (see Table 2-1 on page 11). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered, but the interrupt routine only started after the I flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section "Peripheral Modules").
2.5.1
Interrupt Processing For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two 8bit wide interrupt pending and interrupt active registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. Whenever an interrupt request is detected, the CPU interrupts the program currently being executed, on condition that no higher priority interrupt is present in the interrupt active register. If the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service routine is executed and the current PC is saved on the return stack. An interrupt service routine is completed with the RTI instruction. This instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt-enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is delayed until the interrupt-enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). After a master reset (power-on, brown-out or watchdog reset), the interrupt-enable flag and the interrupt pending and interrupt active registers are all reset.
2.5.2
Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. In MARC4 this is extremely short (taking between 3 to 5 machine cycles depending on the state of the core).
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Figure 2-6. Interrupt Handling
INT7
7 6 Priority Level 5 4 3 2 1 0
Main / Autosleep INT3 INT5
INT7 active RTI
INT5 active RTI
INT2 INT3 active RTI INT2 pending INT2 active RTI SWI0
INT0 pending
INT0 active RTI Main/ Autosleep
Time
Table 2-1.
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Interrupt Priority Table
Priority Lowest | | | | | Highest ROM Address 040h 080h 0C0h 100h 140h 180h 1C0h 1E0h Maskable Yes Yes Yes Yes Yes Yes Yes Yes Interrupt Opcode C8h (SCALL 040h) D0h (SCALL 080h) D8h (SCALL 0C0h) E8h (SCALL 100h) E8h (SCALL 140h) F0h (SCALL 180h) F8h (SCALL 1C0h) FCh (SCALL 1E0h)
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Table 2-2.
Hardware Interrupts
Possible Interrupt Priorities Interrupt Mask 7 RST X # # * * * * * * * * * * * * * * * * * * * * * * * * * * * * Register - - - PAIPR PBIPR P6CR P6CR ITIPR ITIPR T0CR T1CR Bit - - - 3 3 1.0 3.2 0 1 0 0 Function Low level active 1/2 to 2 s time out Level any inputs Any edge, any input Any edge, any input Any edge Any edge 1 of 8 frequencies (8 to 128 Hz) 1 of 8 frequencies (8 to 8192 Hz) Overflow/compare/ end measurement Compare
Interrupt Source NRST external Watchdog Port A coded reset Port A monitor Port B monitor Port 60 external Port 61 external Interval timer INTA Interval timer INTB Timer 0 Timer 1
0
1
2
3
4
5
6
X = Hardwired (neither optional or software configurable) # = Customer mask option (see "Hardware Options") * = Software configurable (see "Peripheral Modules" section for further details)
In the ATAM510, there are eleven hardware interrupt sources which can be programmed to occupy a variety of priority levels. With the exception of the reset sources (RST), each source can be individually masked by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in Table 2-2. 2.5.3 Software Interrupts The programmer can generate interrupts by using the software interrupt instruction (SWI) which is supported in qFORTH by predefined macros named SWI0 to SWI7. The software triggered interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution.
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2.6 Hardware Reset
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, a watchdog time-out, activation of the NRST input, or the occurrence of a coded reset on Port A (see Figure 2-7). A master reset activation will reset the interrupt enable flag, the interrupt pending registers the interrupt active registers and initializes all on-chip peripherals. In this state all ports take on a high resistance input status with deactivated pull-up and pull-down transistors (see Figure 2-9 on page 16) When the reset condition disappears, the hardware configuration previously programmed in the configuration EEPROM (see section "MTP Programming") is loaded into the peripherals so that all port characteristics and pull-up/downs reflect the programmed configuration. This configuration period is immediately followed by a further reset delay time (approximately 80 ms), after which a short call instruction (opcode C1h) to the EEPROM address 008h is performed. This activates the initialization routine $RESET which in turn initializes all necessary RAM variables, stack pointers and peripheral configuration registers. Figure 2-7. Reset Configuration/Start-up Sequence
VDD Pull-up NRST
(1)
= Configuration
Reset delay timer
CPU reset
Power-on reset
VSS VDD
reset code
CODE(1)
Watchdog(1)
Time out Port A I/O
rst
WD reset
Port A
CPU
2.6.1
Power-on Reset The fully integrated power-on reset circuit ensures that the core is held in a reset state until the minimum operating supply voltage has been reached. A reset condition is also generated should the supply voltage drop momentarily below the minimum operating supply. External Reset (NRST) An external reset can be triggered with the NRST pin. To activate an external reset, the pin should be low for a minimum of 4 s. Coded Reset (Port A) The coded reset circuit is connected directly to Port A terminals. By using a mask option, the user can define a hardwired code combination (e.g., all pins low) which, if occurring on Port A, will generate a reset in the same way as the NRST pin.
2.6.2
2.6.3
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Table 2-3.
Multiple Key Reset Options
NO_RST RST2 RST3 RST4 RST5 RST6 RST7 Note:
Not used (default) BPA0 and BPA1 = low BPA0 and BPA1 and BPA2 = low BPA0 and BPA1 and BPA2 and BPA3 = low BPA0 and BPA1 = high BPA0 and BPA1 and BPA2 = high BPA0 and BPA1 and BPA2 and BPA3 = high
If this option is used, the reset is not maskable and will also trigger if the predefined code is written on to Port A by the CPU itself. Care should also be taken not to generate an unwanted reset by inadvertently passing through the reset code on input transitions. This applies especially if the pins have a high capacitive load.
2.6.4
Watchdog Reset The watchdog's function can be enabled via a mask option and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the counter must be regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources. Normal Mode Start-up
Figure 2-8.
NRST
Device status
Reset
Configuration period 250 ms
Power-on reset delay 80 ms
Application program execution
Port status
Program defined
Input mode
Input mode
Input mode
Program defined
Pull-up/ pull-down configuration
Old config.
No pull-up/-down
No pull-up/-down
New configuration
New configuration
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2.7
2.7.1
Clock Generation
Clock Module The clock module generates two clocks. The system clock (SYSCL) supplies the CPU and the peripherals while the lower frequency periphery sub-clock (SUBCL) supplies only the peripherals. The modes for clock sources are programmable with the OS1-bit and OS0-bit in the SCregister and the CCS-bit in the CM-register. The clock module includes 4 different internal oscillator types: two RC-oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins OSC1 and OSC2 provide the interface to connect a crystal either to the 4-MHz, or to the 32-kHz crystal oscillator. SCLIN can be used as an input for an external clock or to connect an external trimming resistor for the RCoscillator 2. All necessary components with the exception of the crystal and the trimming resistor is integrated on-chip. Any one of these clock sources can be selected to generate the system clock (SYSCL). In applications that do not require exact timing, it is possible to use the fully integrated RC-oscillator 1 without any external components. The RC-oscillator 2 is more stable but the oscillator frequency must be trimmed with an external resistor attached between SCLIN and VDD. In this configuration, for system clock frequencies below 2 MHz, the RC-oscillator 2 frequency can be maintained stable with a tolerance of 10% over the full operating temperature and voltage range. The clock module is software programmable using the clock management register (CM) and the system configuration register (SC). The required oscillator configuration can be selected with the OS(1:0)-bits in the SC-register. A programmable 4-bit divider stage allows the adjustment of the system clock speed. A synchronization stage avoids any clock glitches which could be caused by clock source switching. The CPU always requires SYSCL clocks to execute instructions, process interrupts and enter or leave the SLEEP state. Internal oscillators are, depending on the condition of the NSTOP-bit automatically stopped and started where necessary. Special care must however be taken when using an external clock source which is gated by one of the microcontroller port signals. This configuration can hang up if the external oscillator is switched off while the external clock source is still selected. It is therefore advisable in such a case to switch first to the internal RC-oscillator 1 source using the CSS-bit. The external source can then be reselected later when the external oscillator has again been restarted.
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Figure 2-9.
Clock Module
Ext. clock
ExIn ExOut Stop Stop RCOut1 Control IN1 /2 IN2 Divider chain 4Out Stop /8 /2 /2 /2
SCLIN
RCoscillator 1
SC: RC[1:0]
SYSCLmax SYSCL
RC-oscillator2
OSCIN RTrim RCOut2 Stop
to CPU and Timer/ counter
4-MHz oscillator
Oscin Oscout
32-kHz oscillator
OSCOUT Oscin Oscout 32Out Stop SUBCL CM: NSTOP CCS CSS1 CSS0 32 kHz Sleep
SYSCLmax/64
SC:
OS1
OS0
Table 2-4.
Clock Modes
Clock Source for SYSCL Clock Source for SUBCL CCS = 1 CCS = 0 SCLIN/128
Mode 1
OS1 1
OS0 1
CCS = 1 RC-oscillator 1 (internal) RC-oscillator 1 (internal) RC-oscillator 1 (internal) RC-oscillator 1 (internal)
CCS = 0
External input clock SYCLmax/64 RC-oscillator 2 with external trimming resistor 4-MHz oscillator 32-kHz oscillator SYCLmax/64 SYCLmax/64
2
0
1
SYCLmax/64 fXTAL/128
3 4
1 0
0 0
32 kHz
2.7.2 2.7.2.1
Oscillator Circuits and External Clock Input Stage RC-oscillator 1 Fully Integrated For timing insensitive applications, it is possible to use the fully integrated RC-oscillator 1. It operates without any external components and saves additional costs. The RC-oscillator 1 center frequency tolerance is better than 50% over the full temperature and voltage range. A reduction in the application operating supply voltage and temperature ranges will result in improved frequency tolerance. For more detailed information see Figure 7-8 to Figure 7-9 on page 66. The basic center frequency of the RC-oscillator 1 is programmable with the RC1 and the RC0-bits in the SC-register.
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Figure 2-10. RC-oscillator 1
RCoscillator 1 RcOut1 RC0 Stop Control RcOut1 Osc-Stop
RC1
2.7.2.2
External Input Clock The SCLIN pin can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. The maximum system clock frequency fSYSCLmax that the core can operate is fSCLIN/2 (see Figure 2-11). Figure 2-11. External Input Clock
Ext. input clock Ext. Clock SCLIN ExIn Stop ExOut
ExOut Osc-Stop
2.7.2.3
RC-oscillator 2 with External Trimming Resistor The RC-oscillator 2 is a high stability oscillator whereby the oscillator frequency can be trimmed with an external resistor between SCLIN and VDD. In this configuration, as long as the system clock frequency does not exceed 2 MHz, the RC-oscillator 2 frequency can be maintained stable with a tolerance of 10% over the full operating temperature and voltage range. For example: A SYSCLmax frequency of 2 MHz, can be obtained by connecting a resistor Rext = 150 k (see Figure 2-12, Figure 7-6 on page 65 to Figure 7-7 on page 65). Figure 2-12. RC-oscillator 2
VDD Rext SCLIN RTrim Stop RCoscillator 2 RcOut2 RcOut2 Osc-Stop
2.7.2.4
4-MHz Oscillator The integrated system clock oscillator requires an external crystal or ceramic resonator connected between the OSCIN and OSCOUT pins to establish oscillation. All the necessary oscillator circuitry, with the exception of the actual crystal, resonator and the optional C3 and C4 are integrated on-chip.
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Figure 2-13. System Clock Oscillator
C3 OSCIN Oscin 4Out XTAL Cer. Res 4-MHz oscillator Oscout C4 OSCOUT Stop 4Out
Osc-Stop
2.7.2.5
32-kHz Oscillator Some applications require accurate long-term time keeping without putting excessive demands on the CPU or alternatively low resolution computing power. In this case, the on-chip ultra low power 32-kHz crystal oscillator can be used to generate both the SUBCL and/or the SYSCL. In this mode, power consumption can be significantly reduced. The 32-kHz crystal oscillator will key operating (not stopped) during any CPU power-down/SLEEP mode. Figure 2-14. 32-kHz Crystal Oscillator
OSCIN Oscin 32Out XTAL 32 kHz 32-kHz oscillator Oscout OSCOUT 32Out
Note:
Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to stabilize oscillation before the oscillator output is used as system clock. This results in an additional delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal.
2.7.2.6
Quartz Oscillator Configuration If the customer's application necessitates the use of a quartz crystal clock source and this requires capacitive trimming, the trimming capacitors are not integrated into the MTP unlike the ATAR510 and should therefore be connected externally as discrete components between the respective Quartz Crystal terminals (OSCIN, OSCOUT) and VSS.
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2.7.3 Clock Management Register (CM) The clock management register controls the system clock divider chain, as well as the peripheral clock in power-down modes.
Auxiliary register address: 'E'hex Bit 3 CM NSTOP Bit 2 CCS Bit 1 CSS1 Bit 0 CSS0 Reset value: 1111b
NSTOP
Not STOP peripheral clock NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode The 32-kHz crystal oscillator SUBCL clock cannot be stopped NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode Core Clock Select CCS = 1, the internal RC-oscillator 1 generates SYSCL CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the RC-oscillator 2 (with the external resistor) will generate SYSCL dependent on the setting of OS0 and OS1 in the system configuration register Core Speed Select These two bits control the system clock divider chain
CCS
CSS1 (1:0)
Table 2-5.
CSS1 0 0 1 1
Core Speed Select
CSS0 0 1 0 1 Divider 16 8 4 2 Note SYSCLmax/8 SYSCLmax/4 SYSCLmax/2 Reset value = SYSCLmax
2.7.4
System Configuration Register (SC)
Primary register address: 'E'hex Bit 3 SC: write RC1 Bit 2 RC0 Bit 1 OS1 Bit 0 OS0 Reset value: 1111b
Table 2-6.
RC1 0 0 1 1
Internal RC Oscillator 1 Frequency Selection (SYSCLmax)
RC0 0 1 0 1 SYSCLmax at 25C, VDD = 5 V 7.0 MHz (fiRC0) 3.0 MHz (fiRC1) 2.0 MHz (fiRC2) 0.8 MHz (fiRC3) Note - - - Reset value
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OS1, OS0
Oscillator selection bits (in conjunction with the CCS-bit)
Table 2-7.
CCS 0 0 0 0 1 Note:
Oscillator Select
OS1 1 0 1 0 x OS0 1 1 0 0 x 32 kHz SYSCLmax/64 or 32 kHz SYSCLmax/64 SUBCL System Oscillator Selection External input clock at SCLIN RC-oscillator 2 with Rext 4-MHz crystal oscillator 32-kHz crystal oscillator RC-oscillator 1
If the bit CCS = 0 in the CM-register, the RC-oscillator 1 is stopped.
2.7.5
Power-down Modes The ATAM510 incorporates several modes which enable the power consumption to be tailored to a minimum without sacrificing computational power. When the controller exits the lowest priority interrupt task, it reverts to a SLEEP state. This is a CPU shutdown condition which is used to reduce average system power consumption where the CPU itself is only partially utilized. In SLEEP, the CPU clocking system is deactivated whereby the peripherals and associated clock sources may remain active (Standby Mode) or they can also be halted (Halt Mode). In Standby Mode, the peripherals are able to continue operation and if required also generate interrupts which can, along with a reset, reactivate the CPU to bring it out of the sleep state. SLEEP can only be maintained when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. In both Standby and Active modes the current consumption is largely dependent on the frequency of the CPU system clock (SYSCL) and the supply voltage (VDD) (see Figure 7-3 and Figure 7-4 on page 64) while the Halt Mode current is merely controller static leakage current. Selection of Standby or Halt mode is performed by the NSTOP bit in the clock management register (CM). It should be noted that the low power 32-kHz crystal oscillator, if enabled will always remain active in both Standby and Halt modes.
Table 2-8.
Power-down Modes
CPU Core State RUN SLEEP SLEEP RC-Oscillator 1 RC-Oscillator 2 4-MHz Oscillator RUN RUN STOP 32-kHz Oscillator RUN RUN RUN External Input Clock at SCLIN Enabled Enabled Disabled
Mode Active Standby Halt
NSTOP 1 1 0
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2.7.6 Clock Monitor Mode Figure 2-15. Clock Monitoring
NRST
TE SYSCL clocks
BP11 SUBCL clocks
BP10
Oscillator supervisory mode Normal operation
For trimming purposes, the ATAM510 can be put into a clock monitor mode. By forcing the test input (TE) high, the SYSCL clock will appear on BP11 (Port 1, bit 1) and SUBCL clock on Port BP10 (Port 1, bit 0). On releasing the TE pin, the BP10 and BP11 will resume their normal function (see Figure 2-15).
3. Peripheral Modules
3.1 Addressing Peripherals
Accessing the peripheral modules takes place via the I/O bus (see Figure 3-1 on page 22). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme has been adopted which addresses the "primary register" directly. To address the "auxiliary register", the access must be switched with an "auxiliary switching module". Thus, a single IN (or OUT) to the module address will read (or write) into the module primary register. Accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. Byte-wide registers are accessed by multiple IN (or OUT) instructions. Extended addressing is used for more complex peripheral modules, with a larger number of registers. In this case, a bank of up to 16 subport registers are indirectly addressed with the subport address being initially written into the auxiliary register. Please refer to the "HARDC510.SCR" hardware interface file as a programming guideline.
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Figure 3-1.
Example of I/O Addressing
Module ASW Module M1
(Address Pointer) Aux. Reg. Bank of Primary Reg. Subport Fh Subport Eh Aux. Reg.
Module M2
Module M3
2 Auxiliary Switch Module
6
Subport 1 Primary Reg. Subport 0 3 1 5 Primary Reg. 4 7 Primary Reg.
I/O bus
to other modules
Indirect Subport Access (Subport Register Write)
Dual Register Access (Primary Register Write)
Single Register Access (Primary Register Write)
1 2 3
Addr. (M1) Addr. (ASW) OUT Addr. (SPort) Addr. (M1) OUT SPort_Data Addr. (M1) OUT (Subport Register Read)
4
Pirm._Data Addr. (M2) OUT
7
Prim._Data Address (M3) OUT
(Auxiliary Register Write) 5 6 Addr. (M2) Addr. (ASW) OUT Aux._Data Addr. (ASW) OUT (Primary Register Read) 4 Addr. (M2) IN 7 (Primary Register Read) Address (M3) IN
1 2 3
Addr. (M1) Addr. (ASW) OUT Addr. (SPort) Addr. (M1) OUT Addr. (M1) IN (Subport Register Write Byte)
Example of qFORTH Program Code
(Auxiliary Register Read) 5 6 Addr. (M2) Addr. (ASW) OUT Addr. (M2) IN (Auxiliary Register Write Byte) 5 6 Addr. (M2) Addr. (ASW) OUT Aux._Data (lo) Addr. (M2) OUT Aux._Data (hi) Addr. (M2) OUT
1 2 3 3
Addr. (M1) Addr. (ASW) OUT Addr. (SPort) Addr. (M1) OUT SPort_Data (lo) Addr. (M1) OUT SPort_Data (hi) Addr. (M1) OUT
(Subport Register Read Byte) 1 2 3 3 Addr. (M1) Addr. (ASW) OUT Addr. (SPort) Addr. (M1) OUT Addr. (M1) IN Addr. (M1) IN
6
(Auxiliary Register Read) 1 2 Addr. (M1) Addr. (ASW) OUT Addr. (M1) IN
Addr. (ASW) = Auxiliary Switch Module Address Addr. (Mx) = Module Mx Address Addr. (SPort) = Subport Address Prim._Data = data to be written into Primary Register Aux._Data = data to be written into Auxiliary Register Aux._Data (lo) = data to be written into Auxiliary Register (low nibble) Aux._Data (hi) = data to be written into Auxiliary Register (high nibble) SPort_Data (lo) = data to be written into Subport (low nibble) SPort_Data (hi) = data to be written into Subport (high nibble)
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Table 3-1. Peripheral Addresses
Name P0DAT P1DAT PAIPR Auxiliary 3 Auxiliary 4 Auxiliary 5 Auxiliary 6 Auxiliary 7 Auxiliary 8 9 Auxiliary PAICR CWD PBIBR PBICR P4DAT P4DDR P5DAT P5DDR P6DAT P6CR P7DAT P7DDR ASW TCM T0SR TCSUB Subport address 0 1 2 3 4 5 6 7 8 9 A B-F A Auxiliary B Auxiliary C Auxiliary D E Auxiliary F Auxiliary PADAT PADDR PBDAT PBDDR PCDAT PCDDR - SC CM ITFSR ITFSR W/R W W/R W W/R W - W W/R W W T0MO T0CR T1M0 T1CR TCMO TCIOR TCCR TCIP T1CP T1CA T0CP T0CA BZCR W W W W W W W W W R W R W 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b xxxx xxxxb xxxx xxxxb xxxx xxxxb xxxx xxxxb 1111b -- 1111b 1111b 1111b 1111b 1111b 1111b - 1111b 1111b 1111b 1111b Timer 0 mode register Timer 0 control register Timer 1 mode register Timer 1 control register Timer/counter mode register Timer/counter I/O control register Timer/counter control register Timer/counter interrupt priority Timer 1 compare register (byte) Timer 1 capture register (byte) Timer 0 compare register (byte) Timer 0 capture register (byte) Buzzer control register Reserved Port A - data register/pin data Port A - data direction register Port B - data register/pin data Port B - data direction register Port C - data register/pin data Port C - data direction register Reserved System configuration register Clock management register Interval timer frequency select register Interval timer interrupt priority register M2 M2 19 19 34 33 M2 M2 M2 25 25 25 25 25 25 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 41 43 50 51 40 38 38 38 52 52 44 44 55 Write/Read W/R W/R W W R W W W/R W W/R W W/R W W/R W W W/R R W Reset Value 1111b 1111b 1111b 1111b -- 1111b 1111b 1111b 1111b 1111b 1111b 0011b 1111 1111b 1111b 1111b 1111b 1111b 0000b 1111b Register Function Port 0 - data register/input data Port 1- data register/input data Port A - interrupt priority register Port A - interrupt control register Watchdog timer reset Port B- interrupt priority register Port B- interrupt control register Port 4 - data register/pin data Port 4 - data direction register Port 5 - data register/pin data Port 5 - data direction register Port 6 - data register/pin data Port 6 - control register (byte) Port 7- data register/pin data Port 7- data direction register Auxiliary switch register Data to/from subport addressed by TCSUB Timer 0 interrupt status register Timer/counter subport address pointer Module Type M3 M3 M2 M3 M2 M2 M2 M2 M2 ASW M1 M1 M1 See Page 25 25 27 27 14 27 27 25 25 25 25 30 30 25 25 22 22 42 35
Port Address 0 1 2
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3.2
Bi-directional Ports
Overview of Port Features
0 4 no no (2) 500k none yes 1 4 no yes 500k none yes 4 4 yes yes 500k 30k yes 5 4 yes yes 500k 30k no 6 2 yes yes 500k 4k yes External interrupt 7 4 yes yes 500k 30k no A 4 yes yes 500k 30k yes Port monitor/ coded reset B 4 yes yes 500k 30k yes Port monitor C 4 yes yes 500k 30k no
Table 3-2.
Port Address Number of bits
Bit wise programmable direction Output drivers mask configurable(1) Dynamic pull-up/-down typ. (Ohm)(3) Static pull-up/-down typ. (Ohm)(4) Schmitt trigger inputs
Additional functions Notes:
Timer 0
1. Either "open drain down", "open drain up" or CMOS output configuration 2. This output must always be CMOS 3. The Dynamic pull-up/-down transistors are mask programmable and if programmed, are only activated when the associated complementary driver transistor is off. i.e.. A dynamic pull up transistor is only active when the port is either in input mode (both drivers off) or when a logical 1 is written to the port pad (low driver off) in output mode (Figure 3-3 on page 26) 4. The static pull-up/-down transistors are mask programmed and if programmed are always active independent of the port direction or driven state (Figure 3-3 on page 26)
For further data see section "DC Operating Characteristics". All Ports (0, 1, 4, 5, 7, A, B and C with the exception of Port 6) are 4 bits wide. Port 6 has a data width of only 2 bits (bit 0 and bit 1). The ports may be used for data input or output. All ports that can either directly or indirectly generate an interrupt are equipped with Schmitt trigger inputs. A variety of mask options are available such as open drain, open source and full complementary outputs as well as different types of pull-up and pull-down transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address, and the Port Data Direction Register (PxDDR) to the corresponding auxiliary register. All bi-directional ports except Port 0 and Port 1, include a bit wise programmable Data Direction Register (PxDDR) which allows the individual programming of each port bit as input or output. It is also possible to read the pin condition when in output mode. This is a useful feature for selftesting and for collision detection on wired-OR bus systems. There are five different types of bi-directional ports: * Ports 0 and 1: 4-bit wide, bi-directional ports with automatic full bus width direction switching * Port 4: 4-bit wide, bit wise programmable bi-directional port also provides the I/O interface to Timer 0 and the Buzzer * Ports 5, 7 and C: 4-bit wide, bit wise programmable high drive I/O ports * Port 6: 2-bit wide, bit wise programmable bi-directional port with optional static (4 k) pullup/-down and programmable interrupt logic * Ports A and B: 4-bit wide, bit wise programmable bi-directional ports with optional port monitor function
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3.2.1 Port Data Register (PxDAT)
Primary register address: 'Port address' hex Bit 3 PxDAT PxDAT3 Bit 2 PxDAT2 Bit 1 PxDAT1 Bit 0 PxDAT0 Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB, x = Port address 3.2.2 Port Data Direction Register (PxDDR)
Auxiliary register address: 'Port address' hex Bit 3 PxDDR PxDDR3 Bit 2 PxDDR2 Bit 1 PxDDR1 Bit 0 PxDDR0 Reset value: 1111b
Table 3-3.
Port Data Direction Register (PxDDR)
Function BPx0 in input mode BPx0 in output mode BPx1 in input mode BPx1 in output mode BPx2 in input mode BPx2 in output mode BPx3 in input mode BPx3 in output mode
Code: 3 2 1 0 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
3.2.3
Bi-directional Port 0 and Port 1 In this port type, the data direction register is not independently software programmable because the direction of the complete port is switched automatically when an I/O instruction occurs (see Figure 3-2 on page 26). The port can be switched to output mode with an OUT instruction and to input with an IN instruction. The data written to a port will be stored in the output data latches and appears immediately at the port pin following the OUT instruction. After RESET, all output latches are set to 1 and the ports are switched to input mode. An IN instruction reads the condition of the associated pins.
Note: Care must be taken when switching these bi-directional ports from output to input. The capacitive pin loading at this port, in conjunction with the high resistance pull-ups, may cause the CPU to read the contents of the output data register rather than the external input state. This can be avoided by using either of the following programming techniques: Use two IN instructions and DROP the first data nibble. The first IN switches the port from output to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state. Use an OUT instruction followed by an IN instruction. With the OUT instruction, the capacitive load is charged or discharged depending on the optional pull-up /pull-down configuration. Write a 1 for pins with pull-up resistors, and a 0 for pins with pull-down resistors.
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Figure 3-2.
Bi-directional Port 0 and 1
VDD I/O Bus
(1)
VDD (Data out) D Q
(1)
Pull-up
PxDATy R Reset (Direction) OUT S IN R NQ Master reset Q
(1)
BPxy
(1)
(1)
Flash options Port 1 only
Pull-down
3.2.4
Bi-directional Port 5, Port 7 and Port C All bi-directional ports except Port 0 and Port 1, include a bit wise programmable Data Direction Register (PxDDR) which allows the individual programming of each port bit as input or output. It also enables the reading of the pin condition in output mode. The bi-directional Ports 5, 7 and C as well as Port A and Port B are equipped with the same standard I/O logic. However, Port 5, Port 7 and Port C include standard CMOS input stages, whereas Port A, Port B and all other digital signal pins have Schmitt trigger inputs. Port 5 and Port 7 have high current output drive capability for up to 20 mA at 5 V. Whereby the instantaneous sum of the output currents should not exceed 100 mA. Figure 3-3. Bi-directional Ports 5, 7, A, B and C
Port A and Port B with Schmitt trigger I/O Bus Pull-up
(1) (1)
VDD Static Pull-up 30 k at 5 V
(Data out) I/O Bus D S Master reset I/O Bus Q PxDATy
(1)
BPxy
(1)
VDD
D SQ PxDDRy
(1)
(1)
(1)
Static Pull-down
Flash options
Pull-down
(Direction)
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3.2.5 Bi-directional Port A and Port B with Port Monitor Function Port Monitor Module of Port A and Port B
Connected to Ports A and B (x = A or B) PxICR ENx3
BPx3 BPx2 BPx1 BPx0
PRx1 PRx2
Figure 3-4.
ENx2
ENx1
ENx0
IMAx
ITRx
PRx1
PRx2
PxIPR Decoder 2:4
0 0 1 1
0 1 0 1
INT7 INT5 INT3 INT1
INT7 INT5 INT3 INT1
In addition to the standard I/O functions described in section "Bi-directional Port 5, Port 7 and Port C", both Port A (BPA3 - BPA0) and Port B (BPB3 - BPB0) are equipped with Schmitt trigger inputs and a port monitor module. This module is connected across all four port pins (see Figure 3-4) and is intended for monitoring those pins selected by control bits Enx3 - Enx0 and generating an interrupt when the first pin leaves a preselected logical default idle state. This state is defined by control bit ITRx. Transitions on other pins will only cause an interrupt if the other pins have first returned to the idle state. This, for example is useful for interrupt initiated port scanning without the power consuming task of continuously polling for port activity. Using the Port Interrupt Control Register (PxICR), pins can be individually selected. A nonselected pin cannot generate an interrupt. The Port Interrupt Priority Register (PxIPR) allows masking of each interrupt, definition of the interrupt edge and programming of the interrupt priority levels. When programming or reprogramming either of the port monitor control registers, any previously generated interrupt on that port which has not yet been acknowledged by the CPU or an interrupt generated by the reprogramming itself is automatically cleared. Port A can also be used for a mask programmable coded reset. For more information see section "Hardware Reset". The Port Interrupt Priority Registers PAIPR and PBIPR are I/O mapped to the primary address registers of the Port Monitor Module addresses '2'h and '3'h respectively. The Port Interrupt Control Registers PAICR and PBICR are mapped to the corresponding auxiliary registers. 3.2.5.1 Port Monitor Interrupt Priority Register (PxIPR)
x = 'A' (Port A) or 'B' (Port B) (Port A) Primary register address: '2'hex (Port B) Primary register address: '3'hex Bit 3 PxIPR IMx ITRx PRx2..1 IMx Bit 2 ITRx Bit 1 PRx2 Bit 0 PRx1 Reset value: 1111b
Interrupt Mask Interrupt Transition Interrupt Priority code
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Table 3-4.
Code 3210 xx00 xx01 xx10 xx11 x0xx x1xx 0xxx 1xxx
Port Monitor Interrupt Priority Register (PxIPR)
Function Port monitor interrupt priority 7 Port monitor interrupt priority 5 Port monitor interrupt priority 3 Port monitor interrupt priority 1 Port monitor interrupt on falling edge Port monitor interrupt on rising edge Port monitor interrupt enabled Port monitor interrupt disabled
3.2.5.2
Port Monitor Interrupt Control Register (PxICR)
x = 'A' (Port A) or 'B' (Port B) (Port A) Primary register address: '2'hex (Port B) Primary register address: '3'hex Bit 3 PxICR ENx3 Bit 2 ENx2 Bit 1 ENx1 Bit 0 ENx0 Reset value: 1111b
ENx3... 0 port monitor input ENable code
Table 3-5.
Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx
Port Monitor Interrupt Control Register (PxICR)
Function Bit 0 can generate an interrupt Bit 0 cannot generate an interrupt Bit 1 can generate an interrupt Bit 1 cannot generate an interrupt Bit 2 can generate an interrupt Bit 2 cannot generate an interrupt Bit 3 can generate an interrupt Bit 3 cannot generate an interrupt
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3.2.6 Bi-directional Port 6 Figure 3-5. Bi-directional Port 6
VDD Pull-up
(1) (1)
VDD Strong Static Pull-up 4k at 5 V
I/O Bus
VDD (Data out) I/O Bus D Q P6DATy S Master reset IN enable
(1) (1) (1)
BP6y
VDD
(1)
y = 0 or 1
Strong Static Pull-down 4k at 5 V
(1)
Flash options
Pull-down
This 2-bit bi-directional port can be used as a bit wise programmable I/O. The data is LSB aligned so that the two MSB's will not appear on the port pins when written. The port pins can also be used as external interrupt inputs (see Figure 3-5 and Figure 3-6 on page 31). Both interrupts can be masked or independently configured to trigger on either edge. The interrupt priority levels are also configurable. The interrupt configuration and port direction is controlled by the Port 6 Control Register (P6CR). An additional low resistance pull-up transistor (flash option) provides an internal bus pull-up for serial bus applications. In output mode (PxDDR bit = 0), the respective Port Data Register (PxDAT) bit appears on the port pin, driven by an output port driver stage which can be mask programmed as open drain, or full complementary CMOS. With an IN instruction the actual pin state can be read back into the controller at any time without changing the port directional mode. If the output port is flash configured as an open drain driver, the controller is able to receive the external data on this pin without switching into input mode as long as the output transistor is switched off. In input mode (PxDDR bit = 1), the output driver stage is deactivated, so that an IN instruction will directly read the pin state which can be driven from an external source. In this case, the state of the Port Data Register (PxDAT), although not appearing at the pin itself, remains unchanged. High resistance mask selectable pull-up or pull-down transistors are automatically switched onto the port pin in input mode. The Port Data Register is written to the respective port address with an OUT instruction. The Port 6 Data Register (P6DAT) is I/O mapped to the primary address register of address '6'hex and the Port 6 Control Register (P6CR) to the corresponding auxiliary register. The P6CR is a byte wide register and is written by writing the low nibble first and then the high nibble (see section "Addressing peripherals").
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3.2.6.1
Port 6 Data Register (P6DAT)
Primary register address: '6'hex Bit 3 P6DAT Not used Bit 2 Not used Bit 1 P6DAT1 Bit 0 P6DAT0 Reset value: xx11b
The unused bits 2 and 3 are 0, if read. 3.2.6.2 Port 6 Control Register (P6CR)
Auxiliary register address: '6'hex Bit 3 P6CR First write cycle P61IM2 Bit 7 Second write P61PR2 cycle Bit 2 P61IM1 Bit 6 P61PR1 Bit 1 P60IM2 Bit 5 P60PR2 Bit 0 P60IM1 Bit 4 P60PR1 Reset value: 1111b Reset value: 1111b
P6xIM2, P6xIM1 - Port 6x interrupt mode/direction code P6xPR2, P6xPR1 - BP6x interrupt priority code
Table 3-6.
Port 6 Control Register (P6CR)
Auxiliary Address: '6'hex First Write Cycle Second Write Cycle Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx Function BP60 set to priority 1 BP60 set to priority 3 BP60 set to priority 5 BP60 set to priority 7 BP61 set to priority 0 BP61 set to priority 2 BP61 set to priority 4 BP61 set to priority 6
Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx
Function BP60 in input mode interrupt disabled BP60 in input mode rising edge interrupt BP60 in input mode falling edge interrupt BP60 in output mode interrupt disabled BP61 in input mode interrupt disabled BP61 in input mode rising edge interrupt BP61 in input mode falling edge interrupt BP61 in output mode interrupt disabled
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Figure 3-6. Port 6 External Interrupts
INT6
Mask
INT4 INT2 INT0
Edge Data in Dir. Edge Data in Dir. BP60 BP61
Bidir. Port
IN_Enable
INT7 INT5 INT3 INT1
Mask
Bidir. Port
IN_Enable
decode P6CR:
decode
decode
decode I/O bus
CR7
CR6
CR5
CR4
CR3
CR2
CR1 CR0
CR1 CR7 CR6 CR5 INT6 INT4 INT2 INT0 CR4 CR3 INT7 INT5 INT3 INT1
CR0 CR2
Dir.
INT edge
INT disabled
0 0 1 1
0 1 0 1
0 0 1 1
0 1 0 1
0 0 1 1
0 1 0 1
out in in in
-
-
yes no no yes
3.2.7
Bi-directional Port 4 The bi-directional Port 4 is both a bit wise configurable I/O port and provides the external pins for both the Timer 0 and the internal buzzer generator. As an I/O port, it performs in exactly the same way as bi-directional Port 5, 7, A, B and C (see Figure 3-3 on page 26). Two additional multiplexers allow data and port direction control to be passed over to other internal modules (Timer 0 or Buzzer). Each of the four Port 4 pins can be individually switched by the Timer/Counter I/O Register (TCIO). Figure 3-7 shows the internal interfaces to Port 4. Bi-directional Port 4
VDD I/O Bus T0In T0Out I/O Bus D Q P4DATy S Master reset I/O Bus D (Direction) S Q Pull-down Flash options
(1) (1)
Figure 3-7.
VDD
Pull-up
(1) (1)
TCIOy
VDD
(1)
Static Pull-up 30 k at 5 V
BP4y
(Data out)
(1)
VDD
Static Pull-down
P4DDRy TDir
(1)
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3.2.8
TIM1 - Dedicated Timer 1 I/O Pin Figure 3-8. Bi-directional Pin TIM1
VDD T1IN (Timer 1 input) Pull-up
(1)
VDD
(1)
T1OUT (Timer 1 output)
(1)
TIM1
T1Dir (direction control)
(1)
(1) Flash
options
Pull-down
TIM1 is a dedicated bi-directional I/O stage for signal communication to and from Timer 1 in the timer/counter module (see Figure 3-8). It has no I/O bus interface and is not directly accessible from the CPU. Direction control is performed from the timer/counter configuration registers.
3.3
Interval Timers/Prescaler
The interval timers are based on a frequency divider for generating two independent time base interrupts. It is driven by SUBCL generated by the clock module (see Figure 2-9 on page 16) and consists of a 15-stage binary divider and two programmable multiplexers for selecting the appropriate interrupt frequencies for each interrupt source (see Figure 3-9 on page 33). Each multiplexer is completely independent and is controlled by the common Interval Timer Frequency Select Register (ITFSR). Buffer registers store the respective frequency select codes and ensure complete programming independence of each interrupt channel. Interrupt masking and programming of the interrupt priority levels is performed with the aid of the Interval Timer Interrupt Priority Register (ITIPR).
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Figure 3-9. Interval Timers/Prescaler
ITIPR INT5 INT1
Buffer Buffer PRB PRA MIB MIA
ITFSR
FS3
FS2
FS1
FS0
INT6 INT2
Fh Eh Dh INTB Ch 8:1 Bh Mux Ah 9h 8h
8092 Hz 2048 Hz 4096 Hz
8192 Hz 4096 Hz 2048 Hz 1024 Hz 256 Hz 64 Hz 16 Hz 8 Hz 128 Hz 64 Hz
7h 6h 5h INTA 4h 8:1 3h Mux 2h 1h 0h
32 Hz 16 Hz 8 Hz 4 Hz
128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz 2 Hz 1 Hz
1024 Hz 256 Hz
R SUBCL
CK
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
2
10
2
11
2
12
2
13
2
14
2
15
(e.g. SUBCL = 32 kHz)
15-stage binary counter
3.3.1
Interval Timer Registers The Interval Timer Frequency Select Register (ITFSR) is I/O mapped to the primary address register of the prescaler/interval timer address ('F'hex) and the Interval Timer Interrupt Priority Register (ITIPR) to the corresponding auxiliary register. The interrupt masks MIA and MIB enable interrupt masking of INTA and INTB respectively. Each interrupt source can be programmed with PRA and PRB to one of two interrupt priority levels. Disabling both interrupts resets the interval timer. Interval Timer Interrupt Priority Register (ITIPR)
Auxiliary register address (write only): 'F'hex Bit 3 ITIPR PRB Bit 2 PRA Bit 1 MIB Bit 0 MIA Reset value: 1111b
3.3.1.1
PRB - Priority select Interval Timer Interrupt INTB
PRA - Priority select Interval Timer Interrupt INTA MIB - Mask Interval Timer Interrupt INTB MIA - Mask Interval Timer Interrupt INTA
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Table 3-7.
Code 3210 xx11 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
Interval Timer Interrupt Priority Register (ITIPR)
Function Reset prescaler and halt Interrupt A disabled Interrupt A enabled Interrupt B disabled Interrupt B enabled Interrupt A => priority 1 Interrupt A => priority 5 Interrupt B => priority 2 Interrupt B => priority 6
3.3.1.2
Interval Timer Frequency Select Register
Primary register address (write only): 'F'hex Bit 3 ITFSR FS3 Bit 2 FS2 Bit 1 FS1 Bit 0 FS0 Reset value: 1111b
FS3 ... 0 - Frequency select code
Table 3-8.
Code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Interval Timer Frequency Select Register (ITFSR)
Function SUBCL divide by 2 2 2 2 2
15 14
SUBCL = 32 kHz Select 1 Hz Select 2 Hz Select 4 Hz Select 8 Hz Select 16 Hz Select 32 Hz Select 64 Hz Select 128 Hz Select 8 Hz Select 16 Hz Select 64 Hz Select 256 Hz Select 1024 Hz Select 2048 Hz Select 4096 Hz Select 8192 Hz
213
12 11 10
INTA
29 2 2 2
8 12 11
29 INTB 2 2 2 2
7 5 4
23
2
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The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the select code (FS2-FS0). This allows independent programming of interval times for INTA and INTB.
3.4
Watchdog Timer
Figure 3-10. Watchdog Timer
NRST
/ 214 / 215 / 216
*
17-stage binary counter SUBCL Read WDRES Master Reset
Watchdog enable CK R R R R R R R R R R R R R R
*
R R R
*
*
VDD
*
Configurable option
The watchdog timer is a 17-stage binary divider clocked by SUBCL generated within the clock module (see Figure 2-9 on page 16 and Figure 3-10 on page 35). It can only be enabled as a configurable option whereby it must be periodically reset from the application program. The program cannot disable the watchdog. If the CPU finds itself for an extended length of time in SLEEP mode or in a section of program that includes no watchdog reset, then the watchdog will overflow, thus forcing the NRST pin low. This initiates a master reset. The timeout period can be set to 0.5, 1 or 2 seconds (if SUBCL = 32 kHz) by using a configurable option. To reset the watchdog, the program must perform an IN-instruction on the address CWD ('3'hex). No relevant data is usually received. The operation is therefore normally followed by a DROP to flush the data from the stack.
3.5
Timer/Counter Module (TCM)
The TCM consists of two timer/counter blocks (Timer 0 and Timer 1) which can be used separately, or together as a single 16-bit counter/timer (see Figure 3-11 on page 36 and Figure 3-13 on page 40). Each timer can be supplied by various internal or external clock sources. These can be selected and divided under program control using the Timer/Counter Control Register (TCCR), the Timer 0 Control Register (T0CR) and the Timer 1 Control Register (T1CR). Capture and compare registers (T0CA,T1CA,T0CP and T1CP) not only allow event counting, but also the generation of various timed output waveforms including programmable frequencies, modulated melody tones, Pulse Width Modulated (PWM) and Pulse Density Modulated (PDM) output signals. When in one of these signal generation modes, the capture register acts as timer shadow register, the current timer state is frozen whenever read by the CPU. Timer 0 is further equipped to perform a variety of time measurement operations. In this mode the capture register is used together with the gating logic for performing asynchronous, externally triggered snapshot measurements. These measurements include single input pulse width and period measurements and also dual input phase and positional measurements. The mode configuration is set in the Timer 0 and Timer 1 Mode Registers (T0MO and T1MO).
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Each timer represents a single maskable interrupt source (T0INT and T1INT), the priority of which can be configured under program control. A Timer 0 interrupt can be caused by any of three conditions (overflow, compare or end-of-measurement). The associated status register (T0SR) differentiates between these. A status register is not necessary in Timer 1 as an interrupt is caused only on a compare condition. Figure 3-11. Timer/Counter Module
T0IN1 T0IN0 SYSCL MUX 4:1 SUBCL ck Prescaler rst Capture register Gating control up/down T0CA T0SR
Timer 0
Status register
MUX 8:1
Clock control reset
up/down counter
overflow
end-ofmeasurement
Reload control
Compare
T0OUT1 T0CP Compare register Int. enable Output control T0OUT0 T0CR T0MO Int T0INT
T1OUT TCCR TCMO T0OUT0
16-bit mode T1CR T1MO
Int. enable Compare register T1CP carr y T1INT Int Output control T1OUT
Reload control reset
Compare
MUX 8:1
MUX 2:1
Clock control
up/down counter
overflow
SUBCL MUX 4:1 SYSCL T1IN
rst Prescaler ck
T1CA Capture register
Timer 1
< = CPU Read/write registers
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3.5.1 General Timer/Counter Control Registers With the exception of the Timer 0 Interrupt Status Register (T0SR), all the timer/counter registers are indirectly addressed using extended addressing as described in the section "Addressing Peripherals". An overview of all register and subport addresses is shown in Table 3-1 on page 23. The Timer/Counter auxiliary register (TCSUB) holds the subport address of the particular register about to be accessed. Care has to be taken to ensure that this subport access sequence is not interrupted. Please refer to the "HARDC510.SCR" hardware interface file as a programming guideline. 3.5.1.1 Timer/Counter Clock Control Register (TCCR)
Subport address (indirect write access): '6'hex of Port address '9'hex Bit 3 TCCR T1CL2 Bit 2 T1CL1 Bit 1 T0CL2 Bit 0 T0CL1 Reset value: 1111b
T0CL2, T0CL1 - Timer 0 Clock source select T1CL2, T1CL1 - Timer 1 Clock source select
Table 3-9.
Code 3210 xx00 xx01 xx10 xx11 00xx 01xx 10xx 11xx Note:
Timer/Counter Clock Control Register (TCCR)
Function Timer 0 clock = SUBCL Timer 0 clock = SYSCL Timer 0 clock = Timer1 output (T1OUT connected internally) Timer 0 clock = T0IN0 (BP40 ) Timer 1 clock = SUBCL Timer 1 clock = SYSCL Timer 1 clock = Timer 0 output (T0OUT0 connected internally) Timer 1 clock = TIM1
(1)
Direction (TDir) BP40(1) TIM1 out out out in x x x x x x x x out out out in
1. If TCIO0 = low (connects Timer 0 to Port 4)
The Timer/Counter Clock Control Register (TCCR) controls the clock source to both Timer 0 and Timer 1 prescalers. If an external clock source (on BP40 or TIM1) is selected, then the corresponding port direction is automatically switched to input mode (see Figure 3-11 on page 36).
Note: The TCIO0 bit must be set low for the BP40 external timer/counter access.
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3.5.1.2
Timer/Counter Interrupt Priority Register (TCIP) The Timer/Counter Interrupt Priority register (TCIP) is used to configure Timer 0 and Timer 1 interrupt priority levels.
Subport address (indirect write access): '7'hex of Port address '9'hex Bit 3 TCIP T1IP2 Bit 2 T1IP1 Bit 1 T0IP2 Bit 0 T0IP1 Reset value: 1111b
T0IP2, T0IP1 - Timer 0 Interrupt Priority code T1IP2, T1IP1 - Timer 1 Interrupt Priority code
Table 3-10.
Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx
Timer/Counter Interrupt Priority Register (TCIP)
Function Timer 0 interrupt priority 1 Timer 0 interrupt priority 3 Timer 0 interrupt priority 5 Timer 0 interrupt priority 7 Timer 1 interrupt priority 0 Timer 1 interrupt priority 2 Timer 1 interrupt priority 4 Timer 1 interrupt priority 6
3.5.1.3
Timer/Counter I/O Control Register (TCIOR)
Subport address (indirect write access): '5'hex of Port address '9'hex Bit 3 TCIOR TCIO3 Bit 2 TCIO2 Bit 1 TCIO1 Bit 0 TCIO0 Reset value: 1111b
TCIO3...0 - Timer/Counter I/0 mode select
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Table 3-11.
Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
Timer/Counter I/O Control Register (TCIOR)
Function BP40 - standard port mode BP40 - Timer 0 clock input (T0IN0) or Timer 0 output (T0OUT0) BP41 - standard port mode BP41 - Timer 0 gate input (T0IN1) or Timer 0 output (T0OUT1) BP42 - standard port mode BP42 - Buzzer output (BUZ) BP43 - standard port mode BP43 - Buzzer output (NBUZ)
By using the Timer/Counter I/O Control Register (TCIOR) the program can configure the respective Port 4 pins as either standard data I/O ports or as external signal ports for the Timer 0 and Buzzer. The Timer 1 uses a dedicated I/O pin TIM1, whose direction is controlled solely by the TCCR (see Figure 3-12). It should be noted that if a TCIOR bit is set low, then the corresponding port data direction register (P4DDR) bit no longer influences the port direction. In the case of BP40 and BP41, the port direction is then controlled entirely by the timer/counter configuration registers (TCCR,T0MO), while pins BP42 and BP43 become uni-directional buzzer outputs. Figure 3-12. Timer/Counter and Buzzer External Interface
TIMER 0
T0IN0
P4DAT0
T0OUT0
BP40 to CPU
TCIO0 TCCR
Select Ext. Clock
T0IN1
P4DDR0
P4DAT1
T0OUT1
BP41 to CPU
T0MO PWM,PDM
Melody,Counter
TCIO1 P4DDR1 P4DAT2
BUZZER
BUZ
BP42 to CPU
TCIO2 P4DDR2
'0'
P4DAT3
NBUZ
BP43 to CPU
TCIO3 P4DDR3
TIMER 1
T1IN T1OUT
'0'
TIM1
TCCR
Select Ext. Clock
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3.5.1.4
Timer/Counter Mode Register (TCMO)
Subport address (indirect write access): '4'hex of Port address '9'hex Bit 3 TCMO T0NINV TC8 T1STP T0STP T0NINV Bit 2 TC8 Bit 1 T1RST Bit 0 T0RST Reset value: 1111b
Timer 0 output (BP41) appears non-inverted at BP40 Timer/Counter in 8-/16-bit mode Timer 1 Stop/Run Timer 0 Stop/Run
Table 3-12.
Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx
Timer/Counter Mode Register (TCMO)
Function Timer 0 running Timer 0 halted Timer 1 running Timer 1 halted Timer/counter in 16-bit mode Timer/counter in 8-bit mode Inverted output BP41 appears on BP40 (BP40 = NOT BP41) Non-inverted output BP41 appears on BP40 (BP40 = BP41)
3.5.2
Timer/Counter in 16-bit Mode Figure 3-13. 16-bit Mode
Compare Register
Timer 0
Compare Register
Timer 1
Comparator
Carry 8bit/16bit
Comparator
Compare Interrupt
Prescaler
Counter
Prescaler
MUX
Counter
to TIM1
Overflow/compare
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In 16-bit mode, Timer 0 and Timer 1 are cascaded thus forming a 16-bit counter (see Figure 313) whereby, irrespective of the state of Timer 0 interrupt mask bit (T0IM), the Timer 1 counts both Timer 0 overflow and compares interrupt events. These are generated according to the state of the Timer 0 Mode Register as described in the T0MO table. The comparators are also cascaded so that when both Timer 0 and Timer 1 match their respective compare registers, Timer 1 generates both an output signal and a compare interrupt (if unmasked). In measurement modes, only Timer 0 capture register is loaded with Timer 0's contents on an end-of-measurement event. Timer 1 capture register operates solely as a shadow register. There is no 16-bit capture operation, so the user program must check if Timer 1 has incremented between reading the lower and higher byte. Likewise, there is no automatic suppression of spurious interrupts which could conceivably be generated between writing to Timer 0 and Timer 1 compare registers. 3.5.3 Timer 0 Modes The Timer 0 mode configuration is defined in the Timer 0 Mode Register (T0MO). The available modes and the effect on the Timer 0 interrupt and interrupt flags is shown below. In all modes except the position measurement mode, Timer 0 acts as an up-counter, the related clock frequency being defined by the selected clock source and the prescaler division factor. The counter can be reset and halted at any time by the T0RST bit of the TCMO register which also resets all the interrupt status flags and capture registers. Whenever Port 4 BP40 and BP41 pins are required for Timer 0 I/O, then the appropriate TCIOR enable bit must be set low. In this case, the port direction switching is handled automatically by the hardware. In modes where the BP40 is not used as a timer clock input or as a melody envelope output, the BP40 outputs the same signal as that appearing on BP41. With the help of the T0NINV bit of the Timer/Counter Mode Register (TCMO), the BP41 output can be inverted so that BP40 and BP41 form a differential output stage which can be used for directly driving piezo buzzers or small stepper motors. 3.5.3.1 Timer 0 Mode Register (T0MO)
Subport address (indirect write access): '0'hex of Port address '9'hex Bit 3 T0MO T0MO3 Bit 2 T0MO2 Bit 1 T0MO1 Bit 0 T0MO0 Reset value: 1111b
T0MO3 ... 0 - Timer 0 Mode Code
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Table 3-13.
Code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Notes: 1. 2. 3.
Timer 0 Mode Register (T0MO)
Assuming TCIOR1 = TCIOR0 = Low BP40 (3) BP41 cmp Envelope (out) Tone (out) Toggle (out)/Clock (in) Toggle (out)/Clock (in) PDM (out)/Clock (in) PWM (out)/Clock (in) Signal 1 (in) Signal 1 (in) Clock (in) Clock (in) Strobe (out)/Clock (in) Strobe (out)/Clock (in) Clock (in) Tone (out) Tone (out) Toggle (out) Toggle (out) PDM (out) PWM (out) Signal 2 (in) Signal 2 (in) Signal (in) Signal (in) Strobe (out) Strobe (out) Signal (in) y/y y/y y/y n/y n/y n/y n/n (1) n/y n/y y/y n/y n/y n/y Interrupt Set/ T0SR Affected ofl y/y y/y y/y y/y y/y y/y y/y (2) y/y y/y y/y y/y y/y y/y eom n/n n/n n/n n/n n/n n/n y/y n/n y/y y/y n/y n/y y/y y/y
Function Reserved Reserved Modulated melody mode Melody mode Counter-auto reload (50% duty cycle) Counter-free running (50% duty cycle) Pulse density modulation Pulse width modulation Phase measurement Position measurement Low pulse width measurement High pulse width measurement Counter-auto reload (strobe) Counter-free running (strobe) Period measurement (rising edge)
Period measurement (falling edge) Clock (in) Signal (in) The compare interrupt/status flag can only be set when counting up The overflow interrupt/status flag is set on both an overflow or an underflow The BP40 signals can be inverted if T0NINV=0 (TCMO register)
3.5.3.2
Timer 0 Interrupt Status Register (T0SR)
Auxiliary register address (read access): '9'hex Bit 3 T0SR not used Bit 2 T0EOM Bit 1 T0OFL Bit 0 T0CMP Reset value: x000b
Note: The status register is reset automatically when read and also when Timer 0 is reset. T0EOM Timer 0 End Of Measurement status flag T0OFL T0CMP Timer 0 OverFLow status flag Timer 0 CoMPare status flag
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Table 3-14.
Code 3210 xxx1 xx1x x1xx
Timer 0 Interrupt Status Register (T0SR)
Function Timer 0 compare has occurred (Timer 0 = T0CP) Timer 0 overflow or underflow has occurred Timer 0 measurement completed
The interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding interrupt is triggered. Therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked. To see exactly when the flags are set, see T0MO control code, Table 3-13 on page 42. Reading from the timer/counter auxiliary register will access the Timer 0 Interrupt Status Register (T0SR). 3.5.3.3 Timer 0 Control Register (T0CR) The T0CR is responsible for the predivision of the selected Timer 0 input clock (see TCCR). It can be divided or used directly as a clock for the up/down counter. Bit 0 is the mask bit for Timer 0 interrupt.
Subport address (indirect write access): '1'hex of Port address '9'hex Bit 3 T0CR T0FS3 ... 1 T0IM T0FS3 Bit 2 T0FS2 Bit 1 T0FS1 Bit 0 T0IM Reset value: 1111b
- Timer 0 prescaler division factor code - Timer 0 Interrupt Mask
Table 3-15.
Code 3210 xxx1 xxx0 000x 001x 010x 011x 100x 101x 110x 111x
Timer 0 Control Register (T0CR)
Function Timer 0 interrupt disabled Timer 0 interrupt enabled Timer 0 prescaler divide by 256 Timer 0 prescaler divide by 128 Timer 0 prescaler divide by 64 Timer 0 prescaler divide by 32 Timer 0 prescaler divide by 16 Timer 0 prescaler divide by 8 Timer 0 prescaler divide by 4 Timer 0 prescaler bypassed
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3.5.3.4
Timer 0 Compare Register (T0CP) - Byte Write
Subport address (indirect read access): '9'hex of Port address '9'hex Bit 3 T0CP First write cycle T0CP3 Bit 7 Second write T0CP7 cycle Bit 2 T0CP2 Bit 6 T0CP6 Bit 1 T0CP1 Bit 5 T0CP5 Bit 0 T0CP0 Bit 4 T0CP4 Reset value: xxxxb Reset value: xxxxb
T0CP3 ... T0CP0 - Timer 0 Compare Register Data (low nibble) - first write cycle T0CP7 ... T0CP4 - Timer 0 Compare Register Data (high nibble) - second write cycle The compare register T0CP is 8-bit wide and must be accessed as byte wide subport (see section "Addressing Peripherals"). First, the low nibble data is written and is then followed by the high nibble. Any timer interrupts are automatically suppressed until the complete compare value has been transferred. 3.5.3.5 Timer 0 Capture Register (T0CA) - Byte Read
Subport address (indirect read access): '9'hex of Port address '9'hex Bit 7 T0CA First write cycle T0CA7 Bit 3 Second write T0CA3 cycle Bit 6 T0CA6 Bit 2 T0CA2 Bit 5 T0CA5 Bit 1 T0CA1 Bit 4 T0CA4 Bit 0 T0CA0 Reset value: xxxxb Reset value: xxxxb
T0CA7. .. T0CA4 - Timer 0 Capture Register Data (high nibble) - first read cycle T0CA3 ... T0CA0 - Timer 0 Capture Register Data (low nibble) - second read cycle
Note: If the timer is read (in PDM mode only) the bit order will appear reversed, so that T0CA0 = MSB, T0CA1 = MSB - 1 .... T0CA6 = LSB + 1, T0CA7 = LSB.
The 8-bit capture register T0CA is read as byte wide subport. Note, however, unlike writing to the compare register, the high nibble is read first followed by the low nibble. The 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. During this transfer, the timer is free to continue counting. 3.5.3.6 Timer 0 Free Running Counter Modes (Strobe and 50% Duty Cycle) In the free running counter mode, Timer 0 can be used as an event counter for summing external event pulses on BP40, or as a timer with an internal time-based clock. When enabled, the counter will count up generating an output signal on BP41 whenever the counter contents match the compare register (see Figure 3-14 on page 45). This signal can appear either as a strobe pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode. Interrupts (if not masked) are generated every 256 clocks on the overflow condition. The current counter state can be read at any time by reading the capture register,. The compare register has no effect on the counter cycle time and will not influence interrupts.
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Figure 3-14. Timer 0 Free Running Counter Mode
Timer State Overflow Interrupt
255 0 1 2 3 4 56 255 0 1 2 3 4 56 255 0 1 2 3 4 56
strobe
T0OUT1 (BP41)
50% duty cycle
Timer Clock Timer resets on overflow Timer = compare register (= 4)
3.5.3.7
Timer 0 Counter Reload Modes (Strobe and 50% Duty Cycle) As in the free running mode, the counter can also be clocked from either an external signal on BP40 or from an internal clock source. In this mode, the counter repetition period is completely defined by the contents of the compare register (T0CP) (see Figure 3-15). The counter counts up with the selected clock frequency. When it reaches the value held in the compare register, the counter then returns to the zero state. At the same time, depending on the selected timer mode, the BP41 either toggles or generates a strobe pulse. If the Timer 0 interrupt is unmasked, a compare interrupt is also generated. The resultant output frequency fOUT = fIN/2 x (n+1) where n = compare value (n = 1 - 255).
Figure 3-15. Timer 0 Counter Reload Mode
Timer State Compare Interrupt
strobe 0 1 2 3 4 2 4 2 4 0 0 0 3 5 67 1 567 3 567 1
T0OUT1 (BP41)
50% duty cycle
Timer Clock
Timer = compare register (= 7) Resets timer
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3.5.3.8
Melody Mode (with/without Modulation) The non-modulated melody mode is identical to the auto-reload counter (50% duty cycle) mode. The melody tone frequency appearing on BP41 and/or BP40 is determined in exactly the same way as the value written into the comparator register. In the modulated melody mode, the ATAM510 generates two output signals, a melody tone and an envelope pulse (see Figure 316). The tone frequency output on BP41 is generated in exactly the same way as in the simple melody mode. While the envelope pulse on BP40 is a single pulse of a clock period in duration which appears shortly after loading the compare value into the compare register. In this mode, an analog switch is activated between the BP40 and BP41 outputs (see Figure 3-17). With the external capacitor connected, the resultant signal on BP41 exhibits a melody chime effect with an exponential decay.
Figure 3-16. Modulated Melody Mode
Timer State Compare Interrupt T0OUT1 (BP41) T0OUT0 (BP40) Timer Clock 01 2 3 4567 01 234 5 6701 2 345 67 01 234 56 70 1234 5 6 7
New value (= 7) loaded into compare register
Timer = compare register resets timer
Figure 3-17. Modulated Melody Output Circuit
VDD T0OUT0 (melody output) Modulated melody mode T0OUT1 (envelope) VSS T0OUT1 Analog switch BP40 R
(optional)
VDD
10...47 F
Piezo buzzer VSS
BP41
T0OUT0 BP41 BP40
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3.5.3.9 Timer 0 Pulse Width Modulation Mode A pulse width modulated (PWM) signal exhibits a fixed repetition frequency and a variable mark space ratio. It is often used as a simple method for D/A conversion, where the high period is proportional to the digital value to be converted. Therefore by connecting a simple low-pass RC network to the PWM signal, the analog value can be retrieved. Timer 0 generates the PWM signal by comparing the state of the free running up counter with the contents of the compare register (see Figure 3-18). If the result is less than the compare register value, then the BP41 output is high. If the result is greater or equal to the compare register value, then the BP41 output is set low. Thus, the high phase of the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal to a continuous high signal. The PWM signal has a repetition period of 256 clocks, an interrupt (if unmasked) being generated on every overflow event. Care should be taken if the SYSCL clock is used as the PWM clock source because it may stop if the CPU goes into SLEEP mode (see section "Power-Down Modes"). Figure 3-18. Timer 0 Pulse Width Modulation
Timer State Overflow Interrupt t_hi T0OUT1 (BP41) Timer Clock Timer = compare register (= 4) t_hi = (comparator value) x clock period t_low = (255-comparator value) x clock period t_low 255 0 1 2 3 4 255 01 34 255 0 1 3 4
3.5.3.10
Pulse Density Modulation Mode Pulse density modulation (PDM) is also used for simple D/A conversion. Unlike the PWM signal where the high and low signal phases are always continuous during a single repetition cycle, the PDM distributes these evenly as a series of pulses (see Figure 3-19 on page 48). This has the advantage that, if used together with an RC smoothing filter for D/A conversion, either the ripple is less than the PWM, or, for a corresponding ripple error, the filter components can be smaller or the clock frequency lower. To generate the PDM output on BP41, the pulse density is controlled by the contents of the compare register in the same way as the PWM generation. Each of the pulses has a width equal to the counter clock period.
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Figure 3-19. An Example 4-bit PWM/PDM Comparison
Repetition period PWM = 0.25
PWM = 0.75
PDM = 0.25
PDM = 0.75
3.5.3.11
Period Measurement Modes (Rising and Falling Edge) During the period measurement mode, the counter counts the number of either internal or external clocks in one period of the BP41 input signal (see Figure 3-20). Depending on the mode chosen, this will be from rising edge to the next rising edge or conversely, falling edge to the following falling edge. On the trigger edge, the counter state is loaded into the capture register and subsequently reset. The measured value remains in the capture register until overwritten by the following measured value. Interrupts can be generated by either an overflow condition or an end-of-measurement (EOM) event. An EOM event signals to the CPU that a new measured value is present in the capture register and can be read, if required.
Figure 3-20. Period Measurement
Captures and resets timer
EOM Interrupt
t_period t_period
T0IN1 (BP41)
Falling edge triggered
Rising edge triggered
3.5.3.12
Pulse Width Measurement Modes (High and Low) In this mode, the selected clock source is gated to the counter for the duration of each input pulse received on BP41 (see Figure 3-21 on page 49). Whether the measurement takes place during the high or low phase depends on the selected mode. At the end of each pulse, the counter state is loaded into the capture register and subsequently reset. Interrupts can be generated by either an overflow condition or an end-of-measurement (EOM) event. An EOM event signals the CPU that a new measured value is present in the capture register and can be read if required.
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Figure 3-21. Pulse Width Measurement
Captures and resets timer "eom" Interrupt t_low T0IN1 (BP41) t_high
3.5.3.13
Phase Measurement Mode This mode allows the Timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals connected to the BP40 and BP41 pins (see Figure 3-22). The counter clock is gated with the phase misalignment period (tp), during which time the counter increments with the selected clock frequency. This misalignment period is defined as the period during which BP40 is high and BP41 is low. Capturing and resetting of the counter always takes place on the rising edge of BP41. The measured value remains in the capture register until overwritten by the next measurement. Interrupts can be generated by either an overflow condition or an end-ofmeasurement (EOM) event. An EOM event signals to the CPU that a new measured value is present in the capture register and can be read, if required.
Figure 3-22. Phase Measurement
Captures and resets timer
EOM Interrupt
tp tp tp
T0IN0 (BP40) T0IN1 (BP41)
3.5.3.14
Position Measurement Mode This mode is intended for the evaluation of positional sensors with bi-phase output signals. Figure 3-23 on page 50 illustrates a typical positional sensor system which delivers both incremental positional stepping signals and also directional information. The direction can be deduced from the relative phase of the two signals. Therefore if BP40 is high on the rising edge of BP41, the moving mask travels to the left and if it is low then it travels to the right. The direction (left/right) information is used to set the direction of the up/down counter which enables the BP40 pulses to be counted. Assuming that the system has been reset on a reference position, the counter will always hold the absolute current position of the moving mask. This can be read by the CPU if necessary. This mode is the only one in which the counter is allowed to decrement. Therefore, in this case it is possible for both an underflow or an overflow to occur. The overflow interrupt (if unmasked) will trigger on either of these conditions while the compare interrupt on the other hand will only trigger if the counter is counting upwards. To differentiate between an overflow or underflow, the compare value can be set to '0' hex, for example. An
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overflow would then set both the overflow and compare status flags while an underflow sets the overflow status flag only. Figure 3-23. Position Measurement Mode
T0IN0 T0IN1
Typical sensor
light left movement light right movement N+2 N+3 N N-1 N-2
Moving mask Static mask
Timer T0IN0 (BP40) T0IN1 (BP41)
N
N+1
N-3
3.5.4
Timer 1 Modes Timer 1 is meant to perform event counting and timing functions (see Figure 3-11 on page 36). It has, unlike Timer 0, no gated clock or externally triggered capture modes. The counter counts up with an internal or external clock, depending on the state of the Timer 1 Control Register (T1CR) and the Timer/Counter Clock Control Register (TCCR) and generates a compare interrupt whenever the counter matches Timer 1 compare register. This is the only Timer 1 interrupt source. Masking can be performed using the mask bit in the Timer 1 Control Register (T1CR) and priority can be defined in the Timer/Counter Interrupt Priority Register (TCIP). The TIM1 pin is used by the Timer 1 either as clock/event input or timer output. I/O control of the Timer 1 pin TIM1 is controlled entirely by the hardware, therefore if the TIM1 is selected as an external clock or event source (in the TCCR), there can be no Timer 1 signal output. In this case, the timer would be used solely to generate interrupts. In autostop operation, the Timer 1 will halt both itself and Timer 0 whenever the Timer 1 compare value is reached. This feature can be used for example to generate an exact burst of pulses. Both timers will remain stopped until restarted. Restarting is performed in the normal way by setting the appropriate control bits in the Timer/Counter Mode Register (TCM0).
3.5.4.1
Timer 1 Mode Register (T1MO)
Subport address (indirect write access): '2'hex of Port address '9'hex Bit 3 T1MO T1MO3 Bit 2 T1MO2 Bit 1 T1MO1 Bit 0 T1MO0 Reset value: 1111b
T1MO3 ... 0 - Timer 1 Mode Code
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Table 3-16.
Code 3210 xx00 xx01 xx10 xx11 x0xx x1xx 1xxx 0xxx
Timer 1 Mode Register (T1MO)
Function Counter free running (50% duty cycle) Counter auto reload (50% duty cycle) Pulse width modulation Counter auto-reload (strobe output) Increment on falling edge of clock Increment on rising edge of clock Normal operation (no autostop) Autostop operation (Timer 1 stops Timer 2) Compare Interrupt yes yes yes yes - - yes yes
3.5.4.2
Timer 1 Control Register (T1CR) The T1CR is responsible for the predivision of the selected Timer 1 input clock (see TCCR). It can be divided or used directly as clock for the up counter. Bit 0 is the mask bit for the Timer 1 interrupt.
Subport address (indirect write access): '3'hex of Port address '9'hex Bit 3 T1CR T1FS3 ... 1 T1IM T1FS3 Bit 2 T1FS2 Bit 1 T1FS1 Bit 0 T1IM Reset value: 1111b
Timer 1 Prescaler Division Factor Code Timer 1 Interrupt Mask
Table 3-17.
Code 3210 xxx1 xxx0 000x 001x 010x 011x 100x 101x 110x 111x
Timer 1 Control Register (T1CR)
Function Timer 1 interrupt disabled Timer 1 interrupt enabled Timer 1 prescaler divide by 256 Timer 1 prescaler divide by 128 Timer 1 prescaler divide by 64 Timer 1 prescaler divide by 32 Timer 1 prescaler divide by 16 Timer 1 prescaler divide by 8 Timer 1 prescaler divide by 4 Timer 1 prescaler bypassed
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3.5.4.3
Timer 1 Compare Register (T1CP) - Byte Write
Subport address (indirect read access): '8'hex of Port address '9'hex Bit 3 T1CP First write cycle T1CP3 Bit 7 Second write T1CP7 cycle Bit 2 T1CP2 Bit 6 T1CP6 Bit 1 T1CP1 Bit 5 T1CP5 Bit 0 T1CP0 Bit 4 T1CP4 Reset value: xxxxb Reset value: xxxxb
T1CP3 ... T1CP0 - Timer 1 Compare Register Data (low nibble) - first write cycle T1CP7 ... T1CP4 - Timer 1 Compare Register Data (high nibble) - second write cycle The compare register T1CP is 8 bits wide and must be accessed as a byte wide subport (see section "Addressing Peripherals"). The data is written low nibble first, followed by the high nibble. Any timer interrupts are automatically suppressed until the complete compare value has been transferred. 3.5.4.4 Timer 1 Capture Register (T1CA) - Byte Read
Subport address (indirect read access): '8'hex of Port address '9'hex Bit 7 T1CA First write cycle T1CA7 Bit 3 Second write T1CA3 cycle Bit 6 T1CA6 Bit 2 T1CA2 Bit 5 T1CA5 Bit 1 T1CA1 Bit 4 T1CA4 Bit 0 T1CA0 Reset value: xxxxb Reset value: xxxxb
T1CA7. .. T1CA4 - Timer 1 Capture Register Data (high nibble) - first read cycle T1CA3 ... T1CA0 - Timer 1 Capture Register Data (low nibble) - second read cycle The 8-bit capture register T1CA is read as byte wide subport. Note, however, unlike the writing to the compare register, the high nibble is read first followed by low nibble. The 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. During this transfer, the timer is free to continue counting. The previous capture value will be held until the timer is restarted again.
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3.5.4.5 Timer 1 Counter Free Running (50% Duty Cycle) In the free running counter mode, the counter counts up with either an internal or external clock and cycles through all 256 timer states. On the clock following a match between the compare register (T1CR) and the counter, a compare interrupt (if unmasked) is generated and the TIM1 pin is toggled (see Figure 3-23 on page 50).
Figure 3-24. Timer 1 Counter Free Running (50% Duty Cycle)
Timer State Compare Interrupt T1OUT (TIM1) 255 0123456 255 0 1 234 5 6 255 0 1 2 34 5 6
50% duty cycle
Timer Clock
(clock set to rising edge)
Timer = compare register (= 4)
3.5.4.6
Timer 1 Counter Auto Reload (Strobe and 50% Duty Cycle) In the auto-reload mode, the counter counts up with either an internal or external clock. On the clock cycle following a match between the compare register (T1CR) and the counter, a compare interrupt (if unmasked) is generated. The TIM1 output is either strobed or toggled and the counter reset (see Figure 3-25). Therefore, the counter cycle period is defined by the contents of the compare register. In 50% duty cycle mode the frequency of TIM1 is: fTIM1 = fin/2(n+1) where the compare value (n) =1 ... 255
Figure 3-25. Timer 1 Counter Auto Reload
Timer State Compare Interrupt strobe T1OUT (TIM1) 50% duty cycle Timer Clock 0 123 4567 0 123 45 67 0 123 4567 0
(clock set to neg. edge) Timer = compare register (= 7) Resets timer
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3.5.4.7
Timer 1 Pulse Width Modulation The Timer 1 generates the PWM signal by comparing the state of the free running up counter with the contents of the compare register (see Figure 3-26). If the result is less or equal to the compare register value, then the TIM1 output is high. If the result is greater than the compare register value, then the TIM1 output is set low. Thus, the high phase of the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal. The PWM signal has a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every compare event. Care should be taken if SYSCL is used as the PWM clock source. The PWM output may stop if the CPU goes into SLEEP mode depending on the programming of the NSTOP bit in the CMregister. If using this mode of operation it is recommended to set the bit NSTOP =1.
Figure 3-26. Timer 1 Pulse Width Modulation
Timer State 255 0 1 2 3 4 255 0 1 2 3 4 255 0 1 2 3 4
Compare Interrupt t_hi T1OUT (TIM1) Timer Clock t_hi = (comparator value) x clock period t_low = (256-comparator value) x clock period Timer = compare register (= 4) t_low
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3.6 Buzzer Module
The buzzer is a 4 stage frequency divider which divides the SUBCL and depending on the state of the Buzzer Control Register (BZCR) can output one of four frequencies. An external piezo or buzzer can be driven by the complementary buzzer outputs (BUZ and NBUZ) which are directed to Port 4 (BP42 and BP43) under control of the Timer/Counter I/O Register (TCIOR) as shown in Figure 3-11 on page 36. When the buzzer is switched off, both of the buzzer outputs take up the same logical state. This is controlled by the BZOP bit of the BZCR. Figure 3-27. Buzzer Module
BZCR
BZFS2 BZFS1 BZOP BZOF
NBUZ
SUBCL (32 kHz) SUBCL/4 (8 kHz) SUBCL/8 (4 kHz) SUBCL/16 (2 kHz) 4:1 MUX BUZ
SUBCL
CK
4 stage divider R R R R
3.6.0.8
Buzzer Control Register (BZCR)
Subport address (indirect write access): 'A'hex of Port address '9'hex Bit 3 BZCR BZFS2,BZFS2 BZOP BZOF BZFS2 Bit 2 BZFS1 Bit 1 BZOP Bit 0 BZOF Reset value: 1111b
- Buzzer Frequency Select code - Buzzer Output Stop State - Buzzer off/on
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Table 3-18.
Code 3210 xxx0 xxx1 xx0x xx1x 00xx 01xx 10xx 11xx
Buzzer Control Register (BZCR)
Function Buzzer on Buzzer off Buzzer output stop state: BP42 = BP43 = low Buzzer output stop state: BP42 = BP43 = high Buzzer frequency: 32 kHz (= SUBCL) Buzzer frequency: 8 kHz (= SUBCL/4) Buzzer frequency: 4 kHz (= SUBCL/8) Buzzer frequency: 2 kHz (= SUBCL/16)
Figure 3-28. Buzzer Waveform
BUZ
BZOP = 1
NBUZ BUZZER Off
BUZ
BZOP = 0 NBUZ
3.7
MTP Programming
Figure 3-29. Programmer System
In-Circuit Programmer (ICP) Target Programmer Interface (TPI)
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To accommodate the application program and the associated hardware option configuration, the ATAM510 is equipped with 2 on-chip EEPROM memory blocks. These are written via a 6-signal Target Programmer Interface (TPI), comprising of 2 power lines (VDD and VSS), a Program Mode signal (PM) and 3 data lines which are multiplexed onto 3 of the ATAM510 functional pins - BP00, BP01 and BP02 (see Figure 7-1 on page 63). To set up the required hardware options and download these along with the application program into the ATAM510, the customer can be supplied with a dedicated PC based programmer software operating under Windows 95/98 or Windows NT and an In-Circuit Programmer unit (ICP). The ICP is connected to the PC via a standard PC serial interface port and to the target device or application board (for in-system programming) via the TPI flat band cable.
Table 3-19.
Target Programmer Interface Signals
Pin Name PM VDD BP02 BP01 BP00 VSS NC NC NC NC ATAM510 Function Programming mode Input +5 V Supply Port02 (Clock) input Port01 (Data) input Port00 (Data) output Ground Supply Not connected Not connected Not connected Not connected 1 2 3 4 5 6 7 8 9 10
TPI Connector Pin
The state of the ATAM510 PM pin defines the MTP operational mode i.e.. PM = high (Program Mode), PM = low (Normal operation Mode) while the 3 TPI data lines are used to serially load or read the customer's data into or out of the ATAM510. 3.7.1 Application Program The Programmer software requires only the customer's binary *.hex file which is generated by the MARC4 program compiler and also provides the primary data base for emulation. This is displayed on the screen as an editable hexadecimal memory map. Contents of an already programmed device can be read back and displayed on the same hex. form provided that the device's "Read Lock" has not been set. A "Read Lock" Protected device, if read will appear to be full of 'F' hex. Hardware Configuration All hardware configurations are set up within the software's intuitive user interface by selecting the required options from the masks provided. The available configurable hardware options are similar to those of the ATAR510 (see "Hardware Options" section). These affect primarily port configurations, watchdog and coded reset settings. The port driver strengths, although mask programmable in the ATAR510 are not configurable in the MTP, all output drivers being internally "hardwired" to the default "standard drive" strength.
3.7.2
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3.7.3
Read Lock Protection The programmer software incorporates a so called "Read Lock" which can be set by the user. This is provided for customer security purposes and inhibits the reading of the customer's Application Program by unauthorized persons. If set, the "Read Lock" sets a hardware key in the MTP EEPROM which disables reading of the Program/Configuration data. It should be noted that this is a "Read Lock" and not a "Write Lock", so even if the lock is set, it is still possible to overwrite the customer data with new program code. In-System Programming For "in-system programming", the application circuit board must be fitted with a 10-pin male connector to accommodate the TPI connector. To ensure conflict-free access to the target ATAM510 TPI related pins (BP00, BP01, BP02 and PM) it is recommended that these be equipped with jumpers (J5, J4, J3 and J1) to avoid signal contention with other on board driver sources. (see Figure 7-1 on page 63). However, if these can be overdriven, or if Port 0 is not used in the application, then the jumpers can be omitted or replaced by isolating resistors. Prior to connecting the TPI, all other application power supply sources should be disconnected from the application circuit board. Should other on board components either present an excessive power supply load or be unable to withstand the ICP 5-Volt supply voltage, then the VDD power line should also be jumpered (J2). During the programming operation all ports are set into input mode, with the previously programmed pull-up/pull-down transistors deactivated. In normal operational mode, the PM pin is strapped to ground and Port 0 reverts to a port function as described in section "Bi-directional Port 0 and Port 1".
3.7.4
Figure 3-30. In-System Programming
1 2 3 4 5 6 7 8 9 10
VSS NC NC NC NC
1 2 3
VSS BP53 BP52 BP51 BP50 VDD BP43 BP42 BP41 BP40 BP03 BP02 BP01 BP00 TIM1 BPC1 TE BPC0 BP13 BP12 BP11 BP10
BP70 BP71 BP72 BP73 PM SCLIN BP61 BP60 BPB3
44 43 42 41 40 39 38 37 36 3 5 34 33 32 31 30 29 28 27 26 25 24 23 J1 * VSS
Programmer interface
J2 *
4 5 6 7 8 9
10 J3 11 12 13 14 15 16 17 18 19 20 *
ATAM510
Application:
BP00
BP01
BP02
VDD
BPB2 BPB1 BPB0 BPC3 BPC2 AVDD OSCIN OSCOUT NRST BPA0 BPA1 BPA2 BPA3
J4 J5 * *
*Optional jumpers
21 22
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3.8 Noise Considerations
When designing the microcontroller based application, several factors should be taken into consideration to increase noise immunity and reduce electromagnetic emissions (EME). Many such potential problems can be avoided by careful layout of the printed circuit board (PCB). The PCB contains many parasitic components which at first sight are not apparent. PCB tracks can act as antennas or as coupling capacitors. Long stretches of parallel tracks and long high frequency signal lines should thus be avoided wherever possible to minimize the chance of picking up or transmitting unwanted signals. 3.8.1 Noise Immunity The following guidelines will increase system noise immunity: * Unconnected inputs should not be left open. If port pins are not required then it is recommended to set pull-up or pull-down options on these pins. * Special care should be taken when laying out the PCB that interrupt, reset and clock signal lines are kept short and are carefully shielded or have sufficient spacing from other on board noise generating sources. * A quartz crystal should always be located right next to the microcontroller crystal oscillator terminals (OSCIN and OSCOUT), the connections being always very short. This avoids, not only signal coupling onto the clock source, but can also reduces EME. * PCB's should, where economically possible, be equipped with adequate ground planes. * The microcontroller power supply should be decoupled with an electrolytic capacitance (approximate 10 F) in parallel with a ceramic capacitance (approximate 100 nF) situated as close to the microcontroller device as possible. 3.8.2 Electromagnetic Emissions Electromagnetic emissions are caused by rapidly changing electrical currents (dI/dt) in long antenna like connection lines and cables. This can result in electrical interference on other telecommunication devices. These current spikes are more often than not present in the system power supply lines and driver signal lines. The following guide will help to reduce EME: * Keep the length of PCB current switching signal tracks to a minimum.. * Adopt a PCB star power routing system connected at one point. * Many of the microcontroller port outputs can be configured with several drive strengths. This means that a high drive output will switch a signal faster than for example a standard drive output. The resulting change in current in the signal and power lines will also increase, causing an increase in EME. So wherever speed and drive current is not necessary the ports should be configured with the lowest drive possible. * If possible, write the application program to avoid multiple outputs switching at any instant. * Cables can be equipped with ferrite rings to slow current spikes or the system can be encased in a grounded conducting casing.
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4. Absolute Maximum Ratings
Voltages are given relative to VSS. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All inputs and outputs are protected against high electrostatic voltages (4 kV, HBM) or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD). Parameters Supply voltage Input voltage (on any pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (SSO44) Soldering temperature (t 10 s) Symbol VDD VIN tshort Tamb Tstg RthJA Tsld Value -0.3 to +7 VSS -0.3 VIN VDD +0.3 indefinite -40 to +85 -65 to +150 110 260 Unit V V s C C K/W C
5. DC Operating Characteristics
Supply voltage VDD = 5 V, VSS = 0 V, Tamb = -40C to 85C unless otherwise specified. Typical values relate to VDD = 5 V, Tamb = 25C and are for reference only. Parameters Power Supply Supply Voltage Active current Quotient IDD/SYSCL_iR3 Halt current Power-on Reset Threshold Voltage POR threshold voltage Schmitt Trigger Input Voltage: (All Inputs Except Port 5, 7 and C) Negative-going threshold voltage Positive-going threshold voltage Hysteresis (VT+ - VT-) Input Pins: NRST and TE Input voltage LOW Input voltage HIGH Note: VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VIL VIH VSS 0.8 x VDD 0.2 x VDD VDD V V VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VTVT+ VH VSS 0.55 x VDD 0.1 x VDD 0.4 x VDD VDD V V VPOR 0.8 1.0 1.5 V CPU running TestROM at SYSCL_iRC3 CPU running TestROM at SYSCL_iRC3 CPU in sleep mode, NSTOP = 0 VDD IDD IDDQ IHalt 2.2 200 0.25 0.1 6.2 500 0.5 0.5 V A A/kHz A Test Conditions Symbol Min. Typ. Max. Unit
The total sum of all port static output currents must not exceed 100 mA. The sum of all port currents switched at any instant (dI/dt) must not exceed 30 mA.
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5. DC Operating Characteristics (Continued)
Supply voltage VDD = 5 V, VSS = 0 V, Tamb = -40C to 85C unless otherwise specified. Typical values relate to VDD = 5 V, Tamb = 25C and are for reference only. Parameters Input NRST with Pull-up Resistor Input LOW current Input TE with Pull-down Resistor Input HIGH current All Bi-directional Ports and TIM1 Input voltage LOW Input voltage HIGH Dynamic input LOW current (pull-up) Dynamic input HIGH current (pull-down) Output LOW current VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VDD = 2.4 V, VIL= VSS VDD = 5.0 V VDD = 2.4 V, VIH = VDD VDD = 5.0 V VDD = 2.4 V VOL = 0.2 x VDD VDD = 5.0 V VDD = 2.4 V VOH = 0.8 x VDD VDD = 5.0 V VDD = 2.4 V VDD = 5.0 V VDD = 2.4 V VDD = 5.0 V VDD = 2.4 V VDD = 5.0 V VIL VIH IIL IIH IOL 6 -1 IOH -6 IIL IIL IIH IIH IIL IIL -15 -100 15 100 -0.2 -1 0.15 1 -8 -25 -150 25 150 -0.3 -1.35 0.25 1.4 -13 -45 -220 45 220 -0.5 -2 0.5 2 mA A A A A mA mA mA mA 9 -2 13 -4 mA mA VSS 0.8 x VDD -1.0 -5 1.0 5 1 -1.5 -10 1.5 10 2 0.2 x VDD VDD -3.0 -18 2.5 18 4 V V A A A A mA VDD = 5.0 V IIH 1 1.4 2 mA VDD = 2.4 V, VIL= VSS VDD = 5.0 V IIL -1.0 -5 -1.5 -10 -3.0 -18 A A Test Conditions Symbol Min. Typ. Max. Unit
Output HIGH current
Bi-directional Port BP4, BP5, BP7, BPA, BPB and BPC Input LOW current Static pull-up (30 k) Input HIGH current Static pull-down (30 k) Bi-directional Port BP60 and BR61 Input LOW current Static pull-up (4 k)
IIH Input HIGH current VDD = 2.4 V, VIL = VSS VDD = 5.0 V IIH Static pull-down (4 k) Note: The total sum of all port static output currents must not exceed 100 mA. The sum of all port currents switched at any instant (dI/dt) must not exceed 30 mA.
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6. AC Characteristics
Supply voltage VDD = 2.4 to 6.2 V, VSS = 0 V, Tamb = -40C to 85C unless otherwise specified. Typical values relate to VDD = 5 V, Tamb = 25C and are for reference only. Parameters Reset Timing Power-on reset delay NRST input LOW time Interrupt Request Input Timing Interrupt request LOW time Interrupt request HIGH time CPU in SLEEP mode, SC = 0011b, CM = 1100b CPU active, SC = 0011b, CM = 1100b CPU in SLEEP mode, SC = 0111b, CM = 1101b CPU active, SC = 0111b, CM = 1101b CPU in SLEEP mode, SC = 1011b, CM = 1110b CPU active, SC = 1011b, CM = 1110b CPU in SLEEP mode, SC = 1111b, CM = 1111b CPU active, SC = 1111b, CM = 1111b VDD = 5 V 20% CPU in SLEEP mode, 4-MHz crystal active VDD = 2.4 V VDD = 3 V to 5.5 V CPU in SLEEP mode, Rext = 150 k (1%) CPU active, Rext = 150 k VDD = 2.4 V to 5.5 V CPU active/running CPU in SLEEP mode VDD = 2.4 V AVDD = 100 mV tIRL tIRH 50 50 ns ns VDD u VPOR tPOR tNRST 4 80 ms s Test Conditions Symbol Min. Typ. Max. Unit
Internal RC Oscillator (For Additional Characteristics see Figure 7-9 on page 66 to Figure 7-11 on page 67 Standby current of iRC0 SYSCL_iRC0 Standby current of iRC1 SYSCL_iRC1 Standby current of iRC2 SYSCL_iRC2 Standby current of iRC3 SYSCL_iRC3 Stability IiRC0 fSYSCL IiRC1 fSYSCL IiRC2 fSYSCL IiRC3 fSYSCL df/f0 0.60 1.4 1.9 3.5 300 7.0 150 3.0 100 2.0 40 0.80 500 10.5 250 4.5 150 3.0 70 1.3 5 A MHz A MHz A MHz A MHz %
System Clock Crystal/Ceramic Oscillator (For Additional Characteristics see Figure 7-3 on page 64) Standby current Start-up time Stability Ixtal tstartup df/f0 8 0.3 125 10 0.5 A ms ppm
RC Oscillator - External Resistor (For Additional Characteristics see Figure 7-5 on page 65 to Figure 7-8 on page 66) Standby current Frequency Stability 32-kHz Crystal Oscillator Active current HALT current Start-up time Stability IDD32k IHALTx tstartup df/f0 0.1 1.0 10 1.5 1.5 0.3 A A s ppm IxRC fSYSCL df/f0 1.8 2.0 125 2.2 10 A MHz %
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6. AC Characteristics (Continued)
Supply voltage VDD = 2.4 to 6.2 V, VSS = 0 V, Tamb = -40C to 85C unless otherwise specified. Typical values relate to VDD = 5 V, Tamb = 25C and are for reference only. Parameters Test Conditions CPU active, VDD > 2.4 V rise/fall time < 50 ns, see Figure 7-1 on page 63 rise/fall time < 30 ns Symbol Min. Typ. Max. Unit External Clock Input at SCLIN, TIM1 and T0IN SCLIN input clock fSCLIN = 2 x fSYSCL TIM1, T0IN input frequency Number of programming cycles fSYSCL fIN n 1000 4 8 10 MHz MHz Cycles
EEPROM Program/Configuration Memory
7. Crystal Characteristics
Parameters 32-kHz Crystal Crystal frequency Series resistance Static capacitance Dynamic capacitance Load capacitance System Clock Crystal Crystal frequency Series resistance Static capacitance Dynamic capacitance fX RS C0 C1 1.5 4 30 2 3 8 50 4.5 15 MHz pF fF fX RS C0 C1 CL 8 32.768 30 1.5 3 10 12.5 50 kHz k pF fF pF Test Conditions Symbol Min. Typ. Max. Unit
Figure 7-1.
Crystal Equivalent Circuit
OSCIN
OSCOUT
L Equivalent circuit
C1
RS
C0
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Figure 7-2.
Worst Case Minimum/Maximum System Frequency (Using External RC or Crystal Oscillator)
100.000
10.000 fSYSCLmax
fSYSCL (MHz)
1.000
0.100
fSYSCLmin
0.010
0.001 0 1 2 3 4 5 6 7
VDD (V)
Figure 7-3.
IDD = f (fSYSCL), VDD = 3 V
10000.00 VDD = 3 V Tamb = 25C 1000.00 100% active
IDD (A)
100.00 Standby
10.00
1.00 Halt 0.10
0.01 10 100 1000 10000
fSYSCL (kHz)
Figure 7-4.
IDD = f (fSYSCL), VDD = 5 V
10000.00 VDD = 5 V Tamb = 25C 100% active
1000.00
100.00
Standby
IDD (A)
10.00
1.00 Halt 0.10
0.01 10 100 1000 10000
fSYSCL (kHz)
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Figure 7-5. fSYSCL = f (Tamb); External RC
2200 Rext = 150 k 2150 VDD = 5 V 2100
f SYSCL (kHz)
2050
VDD = 3 V
2000
1950
1900 -40 -20 0 20 40 60 80 100
Tamb (C)
Figure 7-6.
fSYSCL = f (Rext)
10000 VDD = 5 V Tamb = 25C
f SYSCL (kHz)
1000
100 10 100 1000
Rext (k)
Figure 7-7.
fSYSCL = f (VDD, Rext)
6000 Rext = 47k Tamb = 25C 4000
5000
f SYSCL (kHz)
3000 Rext = 150 k 2000
1000 Rext = 477 k 0 1.5 2.5 3.5 4.5 5.5 6.5
VDD (V)
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Figure 7-8.
fSYSCL = f (VDD); Internal RC
7000 6000 5000 fiRC0 Tamb = 25C
f SYSCL (kHz)
4000 fiRC1 3000 fiRC2 2000 1000 0 1.5 2.5 3.5 4.5 5.5 6.5 fiRC3
VDD (V)
Figure 7-9.
fSYSCL = f (Tamb), VDD = 3 V
9000 VDD = 3 V 8000 7000 6000 fiRC3
f SYSCL (kHz)
5000 4000 3000 2000 fiRC0 1000 0 -40 -20 0 20 40 60 80 100 fiRC1 fiRC2
Tamb (C)
Figure 7-10. fSYSCL = f (Tamb), VDD = 5 V
10000 9000 8000 7000
fiRC3 VDD = 5 V
f SYSCL (kHz)
6000 5000 4000 3000 2000 1000 0 -40 -20 0 20 40
fiRC2 fiRC1 fiRC0
60
80
100
Tamb (C)
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Figure 7-11. Typical High Output Driver, VDD = 3 V
0 VDD = 3 V -2
-4
IOH (mA)
-6
-8
-10
-12 0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD - VOH (V)
Figure 7-12. Typical Low Output Driver, VDD = 3 V
14 VDD = 3 V 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
IOL (mA)
VOL (V)
Figure 7-13. Typical Low Output Driver, VDD = 5 V
35 VDD = 5 V 30 25
IOL (mA)
20 15 10 5 0 0 1 2 3 4 5
VOL (V)
67
4711B-4BMCU-01/05
Figure 7-14. Typical High Output Driver Pad Layout, VDD = 5 V
0 VDD = 5 V -5 -10
IOH (mA)
-15 -20 -25 -30 -35 0 1 2 3 4 5
VDD - VOH (V)
8. Emulation
The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the analysis of any timing, hardware or software problem. For emulation purposes, all MARC4 controllers include a special emulation mode. In this mode, the internal CPU core is inactive and the I/O buses are available via Port 0 and Port 1 to allow an external access to the on-chip peripherals. The MARC4 emulator uses this mode to control the peripherals of any MARC4 controller (target chip) and emulates the lost ports for the application. The MARC4 emulator can stop and restart a program at specified points during execution, making it possible for the applications engineer to view the memory contents and those of various registers during program execution. The designer also gains the ability to analyze the executed instruction sequences and all the I/O activities. Figure 8-1. MARC4 Emulation
MARC4 emulator Program memory MARC4 emulation-CPU
I/O bus
Emulator target board
MARC4 target chip
Port 0
I/O control
Port 1
Trace memory
CORE
CORE (inactive) Peripherals
Port 0 Control logic
Port 1
Emulation control
SYSCL/ TCL, TE, NRST Application-specific hardware
Personal computer
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9. Ordering Information
Extended Type Number ATAM510x-ILQY ATAM510x-ILSY Note: 1. x = Hardware revision Y = Lead-free Program Memory 4 kB ROM 4 kB ROM Data-EEPROM No No Package SSO44 SSO44 Delivery Taped and reeled Tubes
10. Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications
1
22
69
4711B-4BMCU-01/05
11. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History * Put datasheet in a new template * Features on page 1 changed * Lead-free Logo on page 1 added * Table 1-1 "Pin Description" on pages 3-4 changed * Figure 2-4 "Programming Model" on page 7 changed * Section 2.7.2.5 "32-kHz Oscillator" on page 18 changed * Title Table 2-6 on page 19 added * Table 3-1 "Peripheral Addresses" on page 23 changed * Figure 3-2 "Bi-directional Port 0 and 1" on page 26 changed * Figure 3-3 "Bi-directional Ports 5, 7, A, B and C" on page 26 changed * Figure 3-5 "Bi-directional Port 6" on page 29 changed * Section 3.26 "Bi-directional Port 6" on page 29 changed * Figure 3-7 "Bi-directional Port 4" on page 31 changed * Figure 3-8 "Bi-directional Pin TIM1" on page 32 changed * New heading rows at Table "Absolute Maximum Ratings" on page 60 added * Section 8 "Emulation" on page 68 added *Table "Ordering Information" on page 69 changed
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12. Table of Contents
Features ..................................................................................................... 1 Description ................................................................................................ 1 1 2 Pin Configuration ..................................................................................... 3 MARC4 Architecture ................................................................................ 5
2.1 General Description ..................................................................................................5 2.2 Components of MARC4 Core ...................................................................................6 2.3 Registers ..................................................................................................................7 2.4 ALU ..........................................................................................................................9 2.5 Interrupt Structure ..................................................................................................10 2.6 Hardware Reset .....................................................................................................13 2.7 Clock Generation ....................................................................................................15
3
Peripheral Modules ................................................................................ 21
3.1 Addressing Peripherals ..........................................................................................21 3.2 Bi-directional Ports .................................................................................................24 3.3 Interval Timers/Prescaler .......................................................................................32 3.4 Watchdog Timer .....................................................................................................35 3.5 Timer/Counter Module (TCM) .................................................................................35 3.6 Buzzer Module .......................................................................................................55 3.7 MTP Programming .................................................................................................56 3.8 Noise Considerations .............................................................................................59
4 5 6 7 8 9
Absolute Maximum Ratings .................................................................. 60 DC Operating Characteristics ............................................................... 60 AC Characteristics ................................................................................. 62 Crystal Characteristics .......................................................................... 63 Emulation ................................................................................................ 68 Ordering Information ............................................................................. 69
10 Package Information ............................................................................. 69 11 Revision History ..................................................................................... 70
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